PTP-LP: Using Linear Programming to Increase the Delay Robustness of IEEE 1588 PTP

Puttnies, Henning; Danielis, Peter; Timmermann, Dirk

doi:10.1109/glocom.2018.8647777

Cited by 16 publications

(29 citation statements)

References 15 publications

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“…The authors of [37] agree with the LP formulation from [36] and extend the experiments with more practical hardware impairments, such as oscillator noise and timestamping uncertainty. [37] also contrasts the LP and KF performances under Gaussian and self-similar delays, with the agreeing conclusions that LP can perform better than KF under non-Gaussian delay. Nevertheless, one disadvantage of LP is the relatively high computational cost for solving a new LP problem on every iteration.…”

Section: Model-based Filteringsupporting

confidence: 64%

“…Nevertheless, one disadvantage of LP is the relatively high computational cost for solving a new LP problem on every iteration. Besides, [36] and [37] consider delays in the order of milliseconds, such that their performance figures are poor compared to the nanosecond levels that we target in the remainder of this work.…”

Section: Model-based Filteringmentioning

confidence: 99%

“…The more recent work in [38] augments the LP approach of [37] with the compensation of the slave clock's frequency offset variations due to temperature. The goal is to linearize the slave clock's time offset before LP computations.…”

Section: Model-based Filteringmentioning

confidence: 99%

“…Secondly, the phase noise varies relatively slowly, so that a sufficiently short observation window may capture a constant phase noise contribution to time and frequency offsets. In the end, the model becomes a piecewise linear approximation of (1), as discussed, e.g., in [36], [37].…”

Section: Time and Frequency Offset Processesmentioning

confidence: 99%

See 3 more Smart Citations

Clock Synchronization Algorithms Over PTP-Unaware Networks: Reproducible Comparison Using an FPGA Testbed

Freire

Novaes

Almeida³

et al. 2021

IEEE Access

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This work explores clock synchronization algorithms used to process timestamps from the IEEE 1588 precision time protocol (PTP). It focuses on the PTP-unaware network scenario, where the network nodes do not actively contribute to PTP's operation. This scenario typically imposes a harsh environment for accurate clock distribution, primarily due to the packet delay variation experienced by PTP packets. In this context, it is essential to process the noisy PTP measurements using algorithms and strategies that consider the underlying clock and packet delay models. This work surveys some attractive algorithms and introduces an open-source analysis library that combines several of them for better performance. It also provides an unprecedented comparison of the algorithms based on datasets acquired from a sophisticated testbed composed of field-programmable gate arrays (FPGAs). The investigation provides insights regarding the synchronization performance under various scenarios of background traffic and oscillator stability. INDEX TERMS Clock synchronization, IEEE 1588, partial timing support, precision time protocol.

show abstract

Section: Model-based Filteringsupporting

confidence: 64%

Section: Model-based Filteringmentioning

confidence: 99%

Section: Model-based Filteringmentioning

confidence: 99%

Section: Time and Frequency Offset Processesmentioning

confidence: 99%

See 2 more Smart Citations

Clock Synchronization Algorithms Over PTP-Unaware Networks: Reproducible Comparison Using an FPGA Testbed

Freire

Novaes

Almeida³

et al. 2021

IEEE Access

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“…constant propagation delay and no queuing delay can occur (c.f. [10,11,12]). The time synchronization of the standard is completely based on the master-slave principle.…”

Section: Basicsmentioning

confidence: 99%

A Simulation Model of IEEE 802.1AS gPTP for Clock Synchronization in OMNeT++

Puttnies

Danielis

Janchivnyambuu

et al.

EPiC Series in Computing

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The aim of this paper is to describe a developed simulation model of the gPTP protocol for time synchronization in OMNeT++ using the INET library. gPTP is part of the IEEE TSN standards. Unfortunately, there is currently no simulation model of gPTP available. Therefore, we developed a new simulation model, compared it to results from the state-ofthe-art, and would like to share it with the OMNeT++ community. The simulation model is based on the IEEE 802.1AS specification for full-duplex Ethernet according to a given network topology and use case scenario to analyze the results of the simulation as well as to provide a comparison with results from the state-of-the-art. Time synchronization and propagation delay measurements between time-aware systems are considered and results show that the simulation model works as expected.

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Clock Synchronization Using Linear Programming, Multicasts, and Temperature Compensation

Puttnies

Schweissguth

Timmermann

et al. 2019

2019 IEEE Global Communications Conference (GLOBECOM)

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PTP-LP: Using Linear Programming to Increase the Delay Robustness of IEEE 1588 PTP

Cited by 16 publications

References 15 publications

Clock Synchronization Algorithms Over PTP-Unaware Networks: Reproducible Comparison Using an FPGA Testbed

Clock Synchronization Algorithms Over PTP-Unaware Networks: Reproducible Comparison Using an FPGA Testbed

A Simulation Model of IEEE 802.1AS gPTP for Clock Synchronization in OMNeT++

Clock Synchronization Using Linear Programming, Multicasts, and Temperature Compensation

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