Pseudo Asynchronous Level Crossing <sc>adc</sc> for <sc>ecg</sc> Signal Acquisition

Abstract

A new pseudo asynchronous level crossing analogue-to-digital converter (adc) architecture targeted for low-power, implantable, long-term biomedical sensing applications is presented. In contrast to most of the existing asynchronous level crossing adc designs, the proposed design has no digital-to-analogue converter (dac) and no continuous time comparators. Instead, the proposed architecture uses an analogue memory cell and dynamic comparators. The architecture retains the signal activity dependent sampling operation by generating events only when the input signal is changing. The architecture offers the advantages of smaller chip area, energy saving and fewer analogue system components. Beside lower energy consumption the use of dynamic comparators results in a more robust performance in noise conditions. Moreover, dynamic comparators make interfacing the asynchronous level crossing system to synchronous processing blocks simpler. The proposed adc was implemented in [Formula: see text] complementary metal-oxide-semiconductor (cmos) technology, the hardware occupies a chip area of 0.0372 mm and operates from a supply voltage of [Formula: see text] to [Formula: see text]. The adc's power consumption is as low as 0.6 μW with signal bandwidth from [Formula: see text] to [Formula: see text] and achieves an equivalent number of bits (enob) of up to 8 bits.

A 2.2-<inline-formula> <tex-math notation="LaTeX">$\mu$ </tex-math> </inline-formula>W Cognitive Always-On Wake-Up Circuit for Event-Driven Duty-Cycling of IoT Sensor Nodes

“…As we target stand-alone operation mode, individual trimming of analog external components is not desirable, as it makes it difficult to deploy the solution in real-life applications. To fairly compare different LC-ADC designs a figure-of-merit is introduced in [18] defined as:…”

“…The conversion efficiency of early LC-ADC implementation [11] is mainly limited 1) by the N-bit resistor-ladder digital-to-analog converter (DAC) and 2) by comparators with rail-to-rail input stage capabilities. To achieve higher energy efficiency, a pseudo-asynchronous LC-ADC based on dynamic comparators and a 40 pF analogue memory cell has been proposed in [18]. However this architecture assumes the availability of a clock signal for correct operation, which is not desirable in an always-on self-contained WUC.…”

A 2.1 μW event-driven wake-up circuit based on a level-crossing ADC for pattern recognition in healthcare

“…In this paper an ULP always-on pattern recognition wake-up circuit have been presented. It can be used to wake-up an external high-precision system, contributing to lower the overall [15], where f Nyquist is the Nyquist sampling frequency for the LC-ADC input bandwidth.…”

Arrhythmia Diagnosis by Using Level-Crossing ECG Sampling and Sub-Bands Features Extraction for Mobile Healthcare

“…Conventional ECG processing solutions are based on the Nyquist sampling theory. Systems are time-invariant, which results in a worst-case parameterization [25][26][27][28][29]. A system's computational load and processing activity remain fixed regardless of the incoming ECG signal time-varying nature.…”