Proximity effects in electron beam lithography in SAL 601 resists on a Si-SiO2-Si substrate

Ouabbou, Abdelghafour; Martinez, J. P.; Lalanne, F.; Gerard, P.; Balladore, J.L.

doi:10.1016/0167-9317(93)90005-p

Cited by 4 publications

(1 citation statement)

References 20 publications

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“…In order to control this phenomenon for an N = 4 geometry, we have simulated the e-beam exposure using the Monte Carlo technique described in previous papers [2,11]. Assuming a Gaussian shape of the e-beam, we calculate the energy deposited in the PMMA resist spin-coated onto a Si substrate with 100 nm of SiO 2 at its surface.…”

Section: Optimization Of the E-beam Exposure For Four-electrode Ultra...mentioning

confidence: 99%

Towards four-electrode co-planar metal-insulator-metal nanojunctions down to 10 nm

et al. 2000

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An e-beam nanolithography process with metal lift-off is optimized to produce four-electrode co-planar metal-insulator-metal nanojunctions with an inter-electrode distance down to 10 nm. The e-beam exposure technique is simulated to find the best geometry of the four electrodes. The fabrication process is presented and compared in detail with the simulation. AFM images of four-electrode nanojunctions down to 10 nm are presented. These nanojunctions are well adapted to interconnect hybrid molecular electronic devices.

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Section: Optimization Of the E-beam Exposure For Four-electrode Ultra...mentioning

confidence: 99%

Towards four-electrode co-planar metal-insulator-metal nanojunctions down to 10 nm

et al. 2000

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Fabrication of co-planar metal-insulator-metal solid state nanojunctions down to 5 nm

et al. 1999

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Line edge roughness characterization with a three-dimensional atomic force microscope: Transfer during gate patterning processes

Thiault

Foucher

Tortai

et al. 2005

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

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As critical dimensions (CD) for semiconductor devices shrink to a few tens of nanometers, the line edge roughness (LER) and linewidth roughness (LWR) becomes a critical issue. For this study, we used a new 3D CD-AFM which enables us to characterize LER and LWR along the features after each technological step of standard gate patterning processes. Isolated lines with CDs going from 20nm and 100nm were written with an e-beam lithography tool. First, we transfer the resist mask into silicon to determine the influence of different plasma chemistries on LER. Then, the resist mask is transferred into a standard CMOS gate stack: SiO2 hard mask, polysilicon, dielectric gate. The results after e-beam lithography show that the LWR measured at the bottom of the pattern is higher than the one measured at the middle. It can be attributed to the effect of backscattered electrons. Then, we show that for smaller dimensions, the trimming that occurs during the hard mask opening process weakens the resist and increases drastically the LWR in the polysilicon. This puts forward one limitation of standard processes for aggressive gate patterning. Finally, we do not observe any obvious trend on LER and LWR after the characterization of features coming from two different silicon etching chemistries. This conclusion is surprising. We attributed it to the tip size limitation in sidewall roughness detection on silicon.

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Proximity effects in electron beam lithography in SAL 601 resists on a Si-SiO2-Si substrate

Cited by 4 publications

References 20 publications

Towards four-electrode co-planar metal-insulator-metal nanojunctions down to 10 nm

Towards four-electrode co-planar metal-insulator-metal nanojunctions down to 10 nm

Fabrication of co-planar metal-insulator-metal solid state nanojunctions down to 5 nm

Line edge roughness characterization with a three-dimensional atomic force microscope: Transfer during gate patterning processes

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