Providing fault tolerance through invasive computing

Abstract

As a consequence of technology scaling, today's complex multi-processor systems have become more and more susceptible to errors. In order to satisfy reliability requirements, such systems require methods to detect and tolerate errors. This entails two major challenges: (a) providing a comprehensive approach that ensures fault-tolerant execution of parallel applications across different types of resources, and (b) optimizing resource usage in the face of dynamic fault probabilities or with varying fault tolerance needs of different applications. In this paper, we present a holistic and adaptive approach to provide fault tolerance on Multi-Processor System-on-a-Chip (MPSoC) on demand of an application or environmental needs based on invasive computing. We show how invasive computing may provide adaptive fault tolerance on a heterogeneous MPSoC including hardware accelerators and communication infrastructure such as a Network-on-Chip (NoC). In addition, we present (a) compile-time transformations to automatically adopt well-known redundancy schemes such as Dual Modular Redundancy (DMR) and Triple Modular Redundancy (TMR) for fault-tolerant loop execution on a class of massively parallel arrays of processors called as Tightly Coupled Processor Arrays (). Based on timing characteristics derived from our compilation flow, we further develop (b) a reliability analysis guiding the selection of a suitable degree of fault tolerance. Finally, we present (c) a methodology to detect and adaptively mitigate faults in invasive NoCs.

*‐Predictable MPSoC execution of real‐time control applications using invasive computing

“…Employed appropriately, this significantly improves resource utilization and hence efficiency. Furthermore, the capability to claim resources exclusively (such as processors, memory, and communication) allows to isolate applications and thus make multi‐core program execution predictable concerning non‐functional requirements such as execution time, 7 fault tolerance, 20 or power 21 …”

Invasive computing for timing-predictable stream processing on MPSoCs

“…Whereas, hard requirements must never be violated. Details on security and reliability requirements can be found in [9] and [15].…”

“…Furthermore, hardware faults might occur more often thus making resources temporally or, due to manufacturing variability and aging, even permanently unavailable (cf. [13]), as detailed [15] (part this special issue). It is not possible to cope with these situations by static application mapping.…”