Provably good and practically efficient algorithms for CMP dummy fill

Feng, Chunyang; Zhou, Hai; Yan, Changhao; Tao, Jun; Zeng, Xuan

doi:10.1145/1629911.1630052

Cited by 9 publications

(6 citation statements)

References 12 publications

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“…The designer didn't have any control on the result and this was clearly a blocking point to reach the expected performances of the chip. The flow that has been put in place uses another tool with a significantly different algorithm compared to what is commonly used [4,5]. The results were the ones expected by the designers, both in terms of layout and in terms of efficiency.…”

Section: Qualitymentioning

confidence: 78%

Layout finishing of a 28nm, 3 billions transistors, multi-core processor

Morey-Chaisemartin¹,

Beisser²

2013

SPIE Proceedings

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Designing a fully new 256 cores processor is a great challenge for a fabless startup. In addition to all architecture, functionalities and timing issues, the layout by itself is a bottleneck due to all the process constraints of a 28nm technology. As developers of advanced layout finishing solutions, we were involved in the design flow of this huge chip with its 3 billions transistors. We had to face the issue of dummy patterns instantiation with respect to design constraints. All the design rules to generate the "dummies" are clearly defined in the Design Rule Manual, and some automatic procedures are provided by the foundry itself, but these routines don't take care of the designer requests. Such a chip, embeds both digital parts and analog modules for clock and power management. These two different type of designs have each their own set of constraints. In both cases, the insertion of dummies should not introduce unexpected variations leading to malfunctions. For example, on digital parts were signal race conditions are critical on long wires or bus, introduction of uncontrolled parasitic along these nets are highly critical. For analog devices such as high frequency and high sensitivity comparators, the exact symmetry of the two parts of a current mirror generator should be guaranteed. Thanks to the easily customizable features of our dummies insertion tool, we were able to configure it in order to meet all the designer requirements as well as the process constraints. This paper will present all these advanced key features as well as the layout tricks used to fulfill all requirements. CONSTRAINTS Process constraintswhen performing the layout of any chip, the main set of constraints come from the foundry according to the process specifications. Every constraint is described in the Design Rule Manual. For a 28nm process, many constraints should be met for dummy geometries insertion. We have first, local constraints based on design rules such as spacing and sizes of drawn patterns. This implies that dummy patterns should carefully meet specifications about their shape (width, height, area, aspect ratio...). We then have intra layer density constraints. These constraints may be quite complex:• global density constraint at chip level • local density constraint within a window • density variation between adjacent windows[1]In each case, constraints are made of a minimum and a maximum value.At 28nm node, some inter layer density constraints also start to appear. They will certainly become a key point in future technology nodes (22nm and beyond). With these constraints, not only density constraints should be met for a given process layer, but average densities across multiple layers should be met. As an example, layer 1 and layer 2 should reach a density between 30% and 80%, but the average density of layer 1 and 2 should not exceed 70%. Additionally, it seems that the size of the windows on which these constraints should be met, may vary depending on the layer. Hopefully, we didn't have to face such complex constrai...

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Section: Qualitymentioning

confidence: 78%

Layout finishing of a 28nm, 3 billions transistors, multi-core processor

Morey-Chaisemartin¹,

Beisser²

2013

SPIE Proceedings

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“…One such improvement is developed in [30]. The LP approaches discussed above typically have 𝑂(( 𝑛𝑟 𝑤 ) 2 ) complexity w.r.t the number of variables and constraints thereby making it prohibitive on large layout sizes.…”

Section: Discussionmentioning

confidence: 99%

“…The LP approaches discussed above typically have 𝑂(( 𝑛𝑟 𝑤 ) 2 ) complexity w.r.t the number of variables and constraints thereby making it prohibitive on large layout sizes. [30] proposes a covering linear program (CLP) based formulation wherein the density upper bounds are applied to the tiles instead of the windows. Such an approach lends itself amenable to the more efficient Fully Polynomial Time Approximation Scheme (FPTAS) algorithm [31].…”

Section: Discussionmentioning

confidence: 99%

An Introduction to Metal and Via Fill

Ramkumar

2022

JICS

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In VLSI manufacturing, certain steps such as Chemical Mechanical Polishing (CMP) could affect the functioning of the chip thereby affecting yield. The fill flow adds additional metal and via features to the layout so that the density of metal and vias are uniform across the layout. When metal and vias are uniformly spread across the layout, the side effects of the chemical mechanical polishing step are minimized because variation in polishing depth is minimized. Since the fill process involves addition of metal and via features to the finished layout, this could affect critical layout metrics such as timing. Therefore, it is best if the layout synthesis flow i.e. the place and route flow is made fill-aware to improve performance predictability and enable faster layout convergence. In this paper, we provide a brief overview of the fill problem, algorithms to analyze density and fill synthesis.

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“…The performance of CMP is highly related to the layout density of a given window, and uniform density distribution contributes to high CMP quality [7]. In other words, density variation along windows is very critical, which is also the purpose of introducing dummy fills.…”

Section: Layout Densitymentioning

confidence: 99%

“…As the advancement of technology node, circuits become larger and larger that LP-based method reaches their limitation due to problem sizes. In both [1] and [7], analysis of an example layout with 200µm×200µm windows results in over 160K variables, thus the runtime becomes the bottleneck for LP-based method. Alternative approaches based on Monte Carlo or heuristic algorithms have been proposed.…”

Section: Introductionsmentioning

confidence: 99%

High performance dummy fill insertion with coupling and uniformity constraints

Lin

Pan

2015

Proceedings of the 52nd Annual Design Automation Conference

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In deep-submicron VLSI manufacturing, dummy fills are widely applied to reduce topographic variations and improve layout pattern uniformity. However, the introduction of dummy fills may impact the wire electrical properties, such as coupling capacitance. Traditional tile-based method for fill insertion usually results in very large number of fills, which increases the cost of layout storage. In advanced technology nodes, solving the tile-based dummy fill design is more and more expensive. In this paper, we propose a high performance dummy fill insertion and sizing framework, where the coupling capacitance issues and density variations are considered simultaneously. The experimental results for ICCAD 2014 contest benchmarks demonstrate the effectiveness of our methods.

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Provably good and practically efficient algorithms for CMP dummy fill

Cited by 9 publications

References 12 publications

Layout finishing of a 28nm, 3 billions transistors, multi-core processor

Layout finishing of a 28nm, 3 billions transistors, multi-core processor

An Introduction to Metal and Via Fill

High performance dummy fill insertion with coupling and uniformity constraints

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