Protrusion Study of Through-Silicon-Vias in Dual Anneal-CMP Processes for 3D Integration

Abstract

Through-Silicon Via (TSV) technology is extensively utilized to achieve dense 3D integration. It facilitates the vertical electrical interconnection of different layers of integrated circuits, enabling the creation of sophisticated and space-efficient systems that incorporate a variety of functionalities. This work reports a TSV fabrication with dual anneal-CMP processes to explore the influence of annealing and CMP processes on the evolution of TSV-Cu microstructures and the protrusion. The results show that the dual CMP process can effectively reduce protrusion during high temperatures. The Cu protrusion height increased with the elevation of both the annealing temperature and duration. And it shows good consistency under the high temperature annealing, while shows random phenomenon under 250oC annealing. The phase field model related to TSV grain size was established to quantitatively explore the grain morphology distribution and the thermal mechanical behavior. The results show that the strain in Cu is non-uniform, and the degree of plastic deformation for each grain is closely related to its distribution. The quantity of grains within the TSV is the most important factor affecting the protrusion. As the average grain size expands, the prominence of Cu grain protrusions within TSV intensifies, and the anisotropy of the Cu grains becomes more pronounced. The thermal-mechanical behavior strongly depends on the grain orientation near the top of the TSV, which will lead to some TSV protrusion irregularities. This work may open more opportunities to design high performance TSV preparation methods from the viewpoint of dual CMP process.