Prototyping system for USB3.0 link layer using synthesizable assertions and partial reconfiguration

Krrikyan, Harutyun; Hovhannisyan, Taron; Manukyan, Sergey

doi:10.1109/csitechnol.2015.7358243

Cited by 1 publication

(1 citation statement)

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“…This approach highly relies on directed testing and the stimulus is controlled from higher layer test-sequences. [3], "Prototyping system for USB3.0 link layer using synthesizable assertions and partial reconfiguration", presents problems related to bug detection/localization and coverage calculation. The proposed solution is based on embedding synthesizable assertions into prototype and the experiment was done on USB3.0 link layer FPGA prototype.…”

Section: S S Shankar Et Al In Paper [2] "Synthesizable Verificatimentioning

confidence: 99%

Coverage Driven Functional Testing Architecture for Prototyping System Using Synthesizable Active Agent

Modi

Mehta

2018

VLSICS

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Time and efforts for functional testing of digital logic is big chunk of overall project cycle in VLSI industry. Progress of functional testing is measured by functional coverage where test-plan defines what needs to be covered, and test-results indicates quality of stimulus. Claiming closer of functional testing requires that functional coverage hits 100% of original test-plan. Depending on the complexity of the design, availability of resources and budget, various methods are used for functional testing. Software simulations using various logic simulators, available from Electronic Design Automation (EDA) companies, is primary method for functional testing. The next level in functional testing is pre-silicon verification using Field Programmable Gate Array (FPGA) prototype and/or emulation platforms for stress testing the Design Under Test (DUT). With all the efforts, the purpose is to gain confidence on maturity of DUT to ensures first time silicon success that meets time to market needs of the industry. For any test-environment the bottleneck, in achieving verification closer, is controllability and observability that is quality of stimulus to unearth issues at early stage and coverage calculation. Software simulation, FPGA prototype, or emulation, each method has its own limitations, be it test-time, ease of use, or cost of software, tools and hardware-platform. Compared to software simulation, FPGA prototyping and emulation methods pose greater challenges in quality stimulus generation and coverage calculation. Many researchers have identified the problems of bug-detection / localization, but very few have touched the concept of quality stimulus generation that leads to better functional coverage and thereby uncover hidden bugs in FPGA prototype verification setup. This paper presents a novel approach to address above-mentioned issues by embedding synthesizable active-agent and coverage collector into FPGA prototype. The proposed architecture has been experimented for functional and stress testing of Universal Serial Bus (USB) Link Training and Status State Machine (LTSSM) logic module as DUT in FPGA prototype. The proposed solution is fully synthesizable and hence can be used in both software simulation as well as in prototype system. The biggest advantage is plug and play nature of this active-agent component, that allows its reusability in any USB3.0 LTSSM digital core.

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Section: S S Shankar Et Al In Paper [2] "Synthesizable Verificatimentioning

confidence: 99%