Prototyping platform for performance evaluation of SHA-3 candidates

Abstract

The objective of the SHA-3 NIST competition is to select, from multiple competing candidates, a standard algorithm for cryptographic hashing. The selected winner must have adequate cryptographic properties and good implementation characteristics over a wide range of target platforms, including both software and hardware. Performance evaluation in hardware is particularly challenging because of the large design space, wide range of target technologies, and multitude of optimization criteria. We describe the efforts of three research groups to evaluate SHA-3 candidates using a common prototyping platform. Using a SASEBO-GII FPGA board as a starting point, we evaluate the performance of the 14 remaining SHA-3 candidates with respect to area, throughput, and power consumption. Our approach defines a standard testing harness for SHA-3 candidates, including the interface specifications for the SHA-3 module on the SASEBO testing board.

Pushing the Limits of SHA-3 Hardware Implementations to Fit on RFID

“…There exist several Keccak implementations where most of them have been designed for FPGAs. Highspeed implementations have been reported by J. Strömbergson [39], B. Baldwin et al [3], E. Homsirikamol et al [22], K. Kobayashi et al [31], F. Gürkaynak et al [20], and K. Gaj et al [16,17]. Low-area FPGA designs have been presented by S. Kerckhof et al [29], J.-P. Kaps et al [26], and B. Jungk and J. Apfelbeck [25].…”

ASIC implementations of five SHA-3 finalists

“…Since then, several comprehensive studies in SHA-3 ASIC implementations have been reported [6]- [13]. Guo et al [6] used a consistent and systematic approach to move the SHA-3 hardware benchmark process from the FPGA prototyping by Kobayashi et al [14] to ASIC implementations based 130nm CMOS standard cell technology. Tillich et al [8] presented the first ASIC post-synthesis results using 180nm CMOS standard cell technology with high throughput as the optimization goal and further provided post-layout results [7].…”

High-throughput Hardware Architectures of the JH Round-three SHA-3 Candidate - An FPGA Design and Implementation Approach

“…Regarding hardware implementations of the JH algorithm, to the best of authors' knowledge, there are no previously published works dealing with the JH algorithm itself. However, there are several ones performing comparative analyses among either the round-two candidates (Baldwin et al, 2010); (Henzen et al, 2010); (Tillich et al, 2009); (Matsuo et al, 2010); (Homsirikamol et al, 2010); (Gaj et al, 2010); (Guo et al, 2010a); (Guo et al, 2010b); (Kobayashi et al, 2010), or the round-3 candidates (Jungk et al, 2011); (Kerckhof et al, 2011); (Guo et al, 2011); (Guo et al, 2012); (Jungk, 2011); (Homsirikamol et al, 2011); (Tillich et al, 2010); (Provelengios et al, 2011). The above studies include both FPGA and ASIC CMOS implementations.…”

“…Specifically, FPGA implementations and results are reported in 10 papers (Baldwin et al, 2010); (Matsuo et al, 2010); (Homsirikamol et al, 2010); (Gaj et al, 2010); (Guo et al, 2010a); (Kobayashi et al, 2010); (Jungk et al, 2011); (Jungk, 2011); Homsirikamol et al, 2011;Provelengios et al, 2011).…”