Prototyping pipelined applications on a heterogeneous FPGA multiprocessor virtual platform

Tumeo, Antonino; Branca,; Camerini,; Ceriani,; Monchiero,; Palermo, Gianluca; Ferrandi, Fabrizio; Sciuto, D.

doi:10.1109/aspdac.2009.4796500

Cited by 13 publications

(8 citation statements)

References 12 publications

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“…Various uses of pipelining at system level include exploitation of loop pipelining and pipelined scheduling of tasks on multiprocessor systems to speed up applications [12,13,14,15,16,17,18]. However, none of these works considered processors connected in a pipeline configuration (pipelined MPSoC) which recently has emerged as a viable platform for high throughput implementation of multimedia applications [2,3,4,19,20].…”

Section: Related Workmentioning

confidence: 98%

Low-power adaptive pipelined MPSoCs for multimedia

Javaid

Shafique

Parameswaran

et al. 2011

Proceedings of the 48th Design Automation Conference

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Pipelined MPSoCs provide a high throughput implementation platform for multimedia applications, with reduced design time and improved flexibility. Typically a pipelined MPSoC is balanced at design-time using worst-case parameters. Where there is a widely varying workload, such designs consume exorbitant amount of power. In this paper, we propose a novel adaptive pipelined MPSoC architecture that adapts itself to varying workloads. Our architecture consists of Main Processors and Auxiliary Processors with a distributed run-time balancing approach, where each Main Processor, independent of other Main Processors, decides for itself the number of required Auxiliary Processors at run-time depending on its varying workload. The proposed run-time balancing approach is based on off-line statistical information along with workload prediction and run-time monitoring of current and previous workloads' execution times. We exploited the adaptability of our architecture through a case study on an H.264 video encoder supporting HD720p at 30 fps, where clock-and power-gating were used to deactivate idle Auxiliary Processors during low workload periods. The results show that an adaptive pipelined MPSoC provides energy savings of up to 34% and 40% for clock-and power-gating based deactivation of Auxiliary Processors respectively with a minimum throughput of 29 fps when compared to a design-time balanced pipelined MPSoC.

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Section: Related Workmentioning

confidence: 98%

Low-power adaptive pipelined MPSoCs for multimedia

Javaid

Shafique

Parameswaran

et al. 2011

Proceedings of the 48th Design Automation Conference

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“…While we envision SO(DA) 2 to target CGRAs to take full advantage of quick reconfiguration, and many research prototypes have appeared, actual commercial devices still are upcoming (E.g., Xilinx's Adaptable Computing Acceleration Platform -ACAP). Thus envision that the various toolchain components could be tested and validated by targeting modern FPGAs, proving that abstractions, design space exploration, synthesis techniques, and reconfiguration mechanisms will work [43][44][45]. In seminal work, we have extended HLS methodologies to extract TLP and ILP from OpenMP-like annotated code [9,29,30] and implemented them in an open-source toolchain [5].…”

Section: Proofs Of Conceptmentioning

confidence: 99%

Software defined architectures for data analytics

Castellana

Minutoli

Tumeo

et al. 2019

Proceedings of the 24th Asia and South Pacific Design Automation Conference

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Data analytics applications increasingly are complex workflows composed of phases with very different program behaviors (e.g., graph algorithms and machine learning, algorithms operating on sparse and dense data structures, etc). To reach the levels of efficiency required to process these workflows in real time, upcoming architectures will need to leverage even more workload specialization. If, at one end, we may find even more heterogenous processors composed by a myriad of specialized processing elements, at the other end we may see novel reconfigurable architectures, composed of sets of functional units and memories interconnected with (re)configurable on-chip networks, able to adapt dynamically to adapt the workload characteristics. Field Programmable Gate Arrays are more and more used for accelerating various workloads and, in particular, inferencing in machine learning, providing higher efficiency than other solutions. However, their fine-grained nature still leads to issues for the design software and still makes dynamic reconfiguration impractical. Future, more coarse-grained architectures could offer the features to execute diverse workloads at high efficiency while providing better reconfiguration mechanisms for dynamic adaptability. Nevertheless, we argue that the challenges for reconfigurable computing remain in the software. In this position paper, we describe a possible toolchain for reconfigurable architectures targeted at data analytics.

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“…To maximize the potential of multiprocessors, it is necessary to develop parallel programming. In [44], Tumeo et al present a tool to test and validate pipeline applications.…”

Section: Design Challengesmentioning

confidence: 99%

Reconfigurable Multiprocessor Systems: A Review

Dorta

Jiménez

Martín

et al. 2010

International Journal of Reconfigurable Computing

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Modern digital systems demand increasing electronic resources, so the multiprocessor platforms are a suitable solution for them. This approach provides better results in terms of area, speed, and power consumption compared to traditional uniprocessor digital systems. Reconfigurable multiprocessor systems are a particular type of embedded system, implemented using reconfigurable hardware. This paper presents a review of this emerging research area. A number of state-of-the-art systems published in this field are presented and classified. Design methods and challenges are also discussed. Advances in FPGA technology are leading to more powerful systems in terms of processing and flexibility. Flexibility is one of the strong points of this kind of system, and multiprocessor systems can even be reconfigured at run time, allowing hardware to be adjusted to the demands of the application.

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Prototyping pipelined applications on a heterogeneous FPGA multiprocessor virtual platform

Cited by 13 publications

References 12 publications

Low-power adaptive pipelined MPSoCs for multimedia

Low-power adaptive pipelined MPSoCs for multimedia

Software defined architectures for data analytics

Reconfigurable Multiprocessor Systems: A Review

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