2017
DOI: 10.1109/tns.2017.2693296
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Prototype of the Readout Electronics for WCDA in LHAASO

Abstract: In the Large High Altitude Air Shower Observatory (LHAASO), the Water Cherenkov Detector Array (WCDA) is one of the key parts. The WCDA consists of 3600 Photomultiplier Tubes (PMTs) scattered in a 90000 m 2 area, and both high precision time and charge measurements are required over a large dynamic range from 1 to 4000 Photo Electrons (P.E.). To achieve time measurement precision better than 500 ps RMS, high quality clock distribution and automatic phase compensation are needed among the 400 Front End Electron… Show more

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Cited by 6 publications
(6 citation statements)
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References 21 publications
(16 reference statements)
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“…A 62.5 MHz system clock is fed to the internal PLL inside the FPGA device (XC7A200T-FFG1156 in Artix-7 Series of Xilinx Inc.), which generates four synchronized 375-MHz clock signals with 0°, 45°, 90°, and 135° phases. Using these clocks combined with flip-flops within ISERDESE, a TDC bin size of 333 ps is achieved [16]. We verified our proposed method based on the above WCDA readout electronics in LHAASO.…”
Section: A Charge Measurement In the Lhaaso Wcda Faementioning
confidence: 70%
See 2 more Smart Citations
“…A 62.5 MHz system clock is fed to the internal PLL inside the FPGA device (XC7A200T-FFG1156 in Artix-7 Series of Xilinx Inc.), which generates four synchronized 375-MHz clock signals with 0°, 45°, 90°, and 135° phases. Using these clocks combined with flip-flops within ISERDESE, a TDC bin size of 333 ps is achieved [16]. We verified our proposed method based on the above WCDA readout electronics in LHAASO.…”
Section: A Charge Measurement In the Lhaaso Wcda Faementioning
confidence: 70%
“…The output signal from A3 is digitized by the 12-bits 62.5-Msps ADC. The time measurement is based on the leading edge discrimination and the FPGA (Field Programmable Gate Array)-based TDC technique [16,[24][25][26][27][28][29]. In order to extract the charge information, the output data stream of the ADC was fed to the FPGA for peak detection or waveform integration.…”
Section: A Charge Measurement In the Lhaaso Wcda Faementioning
confidence: 99%
See 1 more Smart Citation
“…To identify each row or column of crystal array, we optimized Gg configurations for our prototype. In general, the measured energy resolution (Res) is mainly affected by the following factors: the crystal and SiPM intrinsic energy jitter (σ0), the noise jitter from the electronics components (σnoise), the jitter from the A/D conversion (σADC) and the digital integration error (σint) [35]:…”
Section: A Structure Of the Multiplexing Networkmentioning
confidence: 99%
“…On the other hand, the FEEs [2] for WCDA 1st pool have been manufactured and have been tested, so we use the FEE to test the PMT afterpulse rate. To simulate the outtrigger test mode, a two channel function generator is used, one channel fed a standard NIM pulse into one FEE channel for reference trigger signal, the other channel gave a positive pulse to trigger a LED which illuminated the PMT.…”
Section: Pos(icrc2019)218mentioning
confidence: 99%