Protein-Assembled Nanocrystal-Based Vertical Flash Memory Devices with Al2O3 Integration

Scalable processes for fabricating non-volatile memory devices using self-assembled 2D arrays of gold nanoparticles as charge storage nodes

“…The rapid shift in flatband voltages during the first 100 cycles is attributed to the generation of stress induced defects in the oxide stack. 28 The endurance profiles were also repeatable across several devices (not shown). Altogether, these results confirm that it is indeed the gold nanoparticles that act as charge storage nodes in these devices.…”

“…Topdown approaches include thermal evaporation, 23 ion implantation, 24 pulsed laser deposition, 25 and rapid thermal annealing induced selforganization of thin films; 26 the industrial adaptation of these approaches is limited by concerns over ability to control the nanoparticle size and density at the sub-20 nm scale, and issues related to gold atom migration at higher annealing temperatures. 27 Bottom-up fabrication of non-volatile flash memory devices by self-assembly of nanoparticle arrays using proteins [28][29][30][31][32] and di-block copolymers [33][34][35] as templates, and using LbL (layer by layer) deposition 36,37 has been recently reported. Templated self-assembly routes involve tedious and costly procedures for generating the templates and are not easily scalable into the sub-20 nm range, due to limitations on the template size, particle size and spacing; whereas, the LbL route is limited by the lack of ordering of the adsorbed nanoparticles at the sub-50 nm scale.…”

Nanoparticle Floating Gate Flash Memories

“…The higher dielectric permittivity of Al 2 O 3 improves cell coupling capacitance. A 2X memory window was obtained in the devices with Al 2 O 3 compared to those with SiO 2 as control oxide at the same gate pulse [8] . We have demonstrated the use of SiGe nanoparticle floating gates on high-k gate tunneling dielectrics to enhance the low voltage/power operation of flash cells, improve the speed and charge retention.…”

“…The vertical design aids in physical scaling, and minimum cell area 4F 2 sq. units becomes achievable when the mesa width equals the minimum line width F and isolation between nearest neighbor cells is also F [8,9] . The gate-all-around (GAA) structure may improve electrical coupling when the mesa width is scaled below 100 nm.…”

“…Nanocrystals were self-assembled on vertical sidewalls employing chaperonin-mediated assembly to obtain a uniform array of nanocrystals [6][7][8][9] . The assembly steps are the same for planar and vertical orientation.…”