Propositional resolution proofs and interpolants derived from them are widely used in automated verification and circuit synthesis. There is a broad consensus that "small is beautiful"-small proofs and interpolants lead to concise abstractions in verification and compact designs in synthesis. Contemporary proof reduction techniques either minimise the proof during construction, or perform a post-hoc transformation of a given resolution proof. We focus on the latter class and present a subsumption-based proof reduction algorithm that extends existing single-pass analyses and relies on a meet-overall paths analysis to identify redundant resolution steps and clauses. We show that smaller refutations do not necessarily entail smaller interpolants, and use labelled interpolation systems to generalise our reduction approach to interpolants. Experimental results support the theoretical claims. 1 Introduction Resolution proofs and interpolants are an integral part of many verificationrelated techniques such as abstraction [24] and model checking [17], vacuity detection [29], synthesis [18, 20], and patch generation [32]. These techniques take advantage of the fact that refutations and interpolants direct the focus to the core of the problem instance (literally and metaphorically). In practice, small refutations provide concise abstractions in model checking [24], and small interpolants enable precise refinement and compact designs in synthesis [20]. Consequently, proof reduction as well as the minimisation of unsatisfiable cores has received ample attention. We roughly group the resulting reduction approaches into two categories: techniques that minimise the proof during construction, and techniques that rely on a post-hoc proof transformation. Algorithms for the extraction of minimal unsatisfiable subsets (such as [25, 4]) typically fall into the former category and rely on iterative calls to a SAT solver.