Proposed Standardization of Heterogenous Integrated Chiplet Models

Mastroianni, Anthony; Kerr, Benjamin; Nasrullah, Jawad; Cameron, Kevin; Wong, Hockshan James; Ratchkov, David; Reynick, Joseph

doi:10.1109/3dic52383.2021.9687611

Cited by 5 publications

(2 citation statements)

References 9 publications

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“…Chiplet technology has emerged as a promising solution to this challenge, allowing multiple specialized chips to be integrated into a more extensive system. [1][2][3][4][5] This approach offers cost reduction, improved yield, shorter design cycles, and better integration. The die-to-die short-reach wireline communication link with high pin/energy efficiency is critical for chiplet technology, which can be applied to memory interconnects and electrical/optical (E/O) interfaces.…”

Section: Introductionmentioning

confidence: 99%

“…As the integrated‐circuit feature sizes approach the physical limit, the cost of realizing high‐performance system‐on‐chip (SOC) increases significantly. Chiplet technology has emerged as a promising solution to this challenge, allowing multiple specialized chips to be integrated into a more extensive system 1–5 . This approach offers cost reduction, improved yield, shorter design cycles, and better integration.…”

Section: Introductionmentioning

confidence: 99%

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A 25‐Gb/s/pin ground‐referenced signaling transceiver with a DC‐coupled equalizer for on‐package communication

Guo,

Chen,

Wang

et al. 2023

Circuit Theory & Apps

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SummaryThis paper proposes a wireline serial link transceiver for on‐package die‐to‐die links based on 12‐nm fin field‐effect transistor (FinFET) technology. The link is crucial for improving the computational performance of larger systems built from chiplets. To achieve high pin/energy efficiency and prevent traditional single‐ended signaling disadvantages, the transceiver adopts single‐ended ground‐reference signaling (GRS) to transfer information. To precompensate for the frequency‐dependent loss, retain the advantages of GRS, and avoid the disadvantages of traditional AC‐coupled equalizer, the transmitter in the transceiver adopts a DC‐coupled switched‐capacitor charge pump equalizer that can transmit GRS and its equilibrium value can be adjusted according to the channel attenuation. This paper proposes a method for timing de‐skew using digital control delay lines to eliminate the timing skew between data and the clock. In addition, this paper presents a duty cycle corrector to avoid duty cycle distortion, with an adjustment range of 44.5% to 52% and a power dissipation of only 30 W. The transceiver has an area of 1.016 0.676 mm2, including one clock lane link and four data lane links. At a nominal 0.8‐V power supply voltage, the aggregate eye‐opening of the measured 25 Gb/s data on an organic substrate channel with an attenuation of −2.2 dB over 6 mm is 0.675 UI, with a bit error rate (BER) of less than 10−12 and an energy efficiency of 1.01 pJ/bit.

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