Proposed Design of 1 KB Memory Array Structure for Cache Memories

Gavaskar, K.; Ragupathy, U. S.; Malini, V.

doi:10.1007/s11277-019-06593-7

Cited by 12 publications

(3 citation statements)

References 23 publications

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“…When compared with binary more states can be represented by quaternary because of its higher radix. With help of the higher radix, the number of interconnections in the circuits can be reduced [12]. As the interconnections are reduced, the complexity of the circuit is minimized.…”

Section: Existing Methodsmentioning

confidence: 99%

Design of Low Power Multiplier with Less Area Using Quaternary Carry Increment Adder for New-Fangled Processors

Gavaskar¹,

Malathi²,

Ravivarma³

et al. 2022

Wireless Pers Commun

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Multiplication is one of the basic functions in Digital Signal Processing (DSP) applications. Multiplier plays an important role in Arithmetic and Logic Unit (ALU), which is a critical element in the processors. The e ciency of the multiplier takes part a crucial task in the execution of the processor. The performance of the multiplier depends on the adder circuit. The addition operation is the fundamental operation used in most of the digital circuits. Power, delay and area are the main issues in VLSI circuits. E ciency of a VLSI circuit can be improved by rectifying any of these issues. Quaternary Signed Digits (QSD) placed on adders have better e ciency when compared to traditional binary logic. QSD based Carry Look Ahead (CLA) Adder is used to increase the e ciency with reference to power and delay. The proposed method uses Quaternary Carry Increment Adder in order to improve the power and reduce the delay of the existing Quaternary Carry Look Ahead Adder. Tanner EDA is the simulation tool used to design the circuits and the power, delay and power-delay product of the designed circuits are measured using it.

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Section: Existing Methodsmentioning

confidence: 99%

Design of Low Power Multiplier with Less Area Using Quaternary Carry Increment Adder for New-Fangled Processors

Gavaskar¹,

Malathi²,

Ravivarma³

et al. 2022

Wireless Pers Commun

Self Cite

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“…For SRAM designs in aerospace applications, the soft error rate, power consumption, size, and delay are the most critical metrics to consider. In addition, SRAM cells take up much space in the device on the chip [24][25][26][27].…”

Section: Introductionmentioning

confidence: 99%

Low-Power SRAM Cell and Array Structure in Aerospace Applications: Single-Event Upset Impact Analysis

Gavaskar¹,

Sivaranjani²,

Elango³

et al. 2022

Wireless Pers Commun

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One of the most critical functions of a computer is memory, as it would be impossible for it to function e ciently without it. The main memory of a computer is known as Random Access Memory (RAM). It stores operating system software, applications, and other data for the central processor unit (CPU) to perform operations swiftly and e ciently. Unfortunately, traditional static RAM (SRAMs) in aerospace applications suffers from high soft error issues such as Single Event Upset (SEU). To overcome the soft error problems, many Radiation-Hardened-Based Designs (RHBD) and Radiation-Hardened-Polar Designs (RHPD) have been developed, such as 12T We-Quatro, twelve-transistor (12T) Dice SRAM cells, and so on. However, they consume more total and static power, as well as have more delay and area. In this article, an RHPD and RHBD 12T SRAM cell is proposed to reduce power dissipation and area overhead. Compared to RHPD, the RHBD 12T SRAM cell devours less total and static power, and RHPD cells have less delay. The proposed SRAM cell is implemented in the 32 x 32 array architecture. The power consumption of a 32 x 32 SRAM array with a 12T RHBD SRAM cell is 1.33mW, which is 10.1% less than a 32 x 32 SRAM array with a 12T RHPD SRAM array is 4.23mW. Cadence virtuoso 6.1.5 at 45 nm Generic Process Design Kit (GPDK) technology le is used to simulate the comparative analysis for the SRAM cell.

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“…All the methods of the AES algorithm are made key-dependent by using this method to increase security. On the other hand, the area consumption and the area utilized by the algorithm have been raised [12][13][14][15][16].…”

mentioning

confidence: 99%

AES Algorithm using Dynamic Shift Rows, Sub Bytes and Mix Column Operations for Systems Security wih Optimal Delay

Gavaskar

Ragupathy

Ravivarma

et al. 2022

Preprint

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In the digital world, all the transmitted data is vulnerable and prone to attack. To reduce the vulnerability, security is needed for the data. The security of the data can be enhanced by implementing cryptographic techniques. Thus, the sender and the receiver can only view the data by implementing cryptography, whereas a third party cannot intervene. Cryptographic algorithms are used in the IoT, online banking, Web servers, etc. The Advanced Encryption Standard (AES) is symmetric-key cryptography; it has the same key for both the encryption and decryption process. Each step in the AES algorithm is modified by using the key generated for each round, so each step of the AES is made key-dependent. This gives the dynamic AES algorithm. However, the delay and area are comparatively higher than the traditional method. Thus, the proposed method involves combining two steps, the sub-byte transformation and shifting rows. By doing this, the registers used to store the sub-byte data are removed. Thus, eliminating registers leads to less area consumption. Simulation is done using Verilog HDL in ModelSim and the synthesis is done in Xilinx Design Suite.

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Proposed Design of 1 KB Memory Array Structure for Cache Memories

Cited by 12 publications

References 23 publications

Design of Low Power Multiplier with Less Area Using Quaternary Carry Increment Adder for New-Fangled Processors

Design of Low Power Multiplier with Less Area Using Quaternary Carry Increment Adder for New-Fangled Processors

Low-Power SRAM Cell and Array Structure in Aerospace Applications: Single-Event Upset Impact Analysis

AES Algorithm using Dynamic Shift Rows, Sub Bytes and Mix Column Operations for Systems Security wih Optimal Delay

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