Proposed Adder and Modified LUT Bit Parallel Unrolled CORDIC Circuit for an Application in Mobile Robots

Velrajkuma, P.; Senthilpar, C.; Ramanamurt, G.; Wong, Elaine

doi:10.3923/ajsr.2013.666.678

Cited by 3 publications

(1 citation statement)

References 8 publications

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“…It consists of three inputs and two outputs. In this design, the three inputs have been designated as 'A', 'B' and 'C' (Velrajkumar et al, 2013). The LVS is analysed for the designed full adder circuit by using various methods.…”

Section: Methodsmentioning

confidence: 99%

Low Energy, Improved Speed and High Throughput CORDIC Cell to Improve Performance of Robots’ Processor

Velrajkuma¹,

Senthilpar²,

Murthy³

et al. 2015

Asian J. of Scientific Research

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Robots are used in various real-time applications. The speed constraint in robotic system applications requires a real-time interface operation; this is a recent target in robotic research. The cost and size of a robotic system is often determined by hardware-based solutions. The coordinate Rotation Digital Computer (CORDIC) technique allows for an efficient execution of functions, such as inverse tangents and vector rotations, in the hardware. The CORDIC algorithm is very well suited for VLSI implementation due to the simplicity of the involved operations. This study proposed a full-adder based bit parallel iterative CORDIC circuit to improve the performance of robots' processor. The proposed full-adder and CORDIC circuit are designed and their layouts are generated by VLSI CAD tool. The parametric analysis is done using by BSIM4 analyzer. The output parameters such as propagation delay, area and power dissipation are calculated from simulated results of CORDIC cell. The proposed adder based CORDIC circuit designed for low energy, improved speed, low EPI and high throughput. The simulated result of proposed adder based CORDIC circuit is compared with other published CORDIC circuits. From the analysis of these simulated results, it was found that proposed adder based CORDIC circuit gives better performance in terms of power, propagation delay, speed, EPI and throughput than other published results. The results are extended to analysis of temperature coefficient, thermal conductivity and thermal flux for CORDIC cells' chip. The proposed circuit gives better tolerance of temperature and less leakage current than other adder based CORDIC cell.

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Section: Methodsmentioning

confidence: 99%

Low Energy, Improved Speed and High Throughput CORDIC Cell to Improve Performance of Robots’ Processor

Velrajkuma¹,

Senthilpar²,

Murthy³

et al. 2015

Asian J. of Scientific Research

Self Cite

View full text Add to dashboard Cite

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Performance Analysis of ST-Type Module for Nearest Level Control Scheme Based Asymmetric 17-Level Multilevel Inverter Fed Single-Phase Induction Motor

Ramesh

Hari

Iqbal

et al. 2020

Intelligent Computing and Communication

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A Novel Sample Based Quadrature Phase Shift Keying Demodulator

Moubark

Ali

2014

The Scientific World Journal

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This paper presents a new practical QPSK receiver that uses digitized samples of incoming QPSK analog signal to determine the phase of the QPSK symbol. The proposed technique is more robust to phase noise and consumes up to 89.6% less power for signal detection in demodulation operation. On the contrary, the conventional QPSK demodulation process where it uses coherent detection technique requires the exact incoming signal frequency; thus, any variation in the frequency of the local oscillator or incoming signal will cause phase noise. A software simulation of the proposed design was successfully carried out using MATLAB Simulink software platform. In the conventional system, at least 10 dB signal to noise ratio (SNR) is required to achieve the bit error rate (BER) of 10−6, whereas, in the proposed technique, the same BER value can be achieved with only 5 dB SNR. Since some of the power consuming elements such as voltage control oscillator (VCO), mixer, and low pass filter (LPF) are no longer needed, the proposed QPSK demodulator will consume almost 68.8% to 99.6% less operational power compared to conventional QPSK demodulator.

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Proposed Adder and Modified LUT Bit Parallel Unrolled CORDIC Circuit for an Application in Mobile Robots

Cited by 3 publications

References 8 publications

Low Energy, Improved Speed and High Throughput CORDIC Cell to Improve Performance of Robots’ Processor

Low Energy, Improved Speed and High Throughput CORDIC Cell to Improve Performance of Robots’ Processor

Performance Analysis of ST-Type Module for Nearest Level Control Scheme Based Asymmetric 17-Level Multilevel Inverter Fed Single-Phase Induction Motor

A Novel Sample Based Quadrature Phase Shift Keying Demodulator

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