Proposal and Study for an Architecture Hardware∕software for the Implementation of the Standard H264

Messaoudi, Kamel; Toumi, Salah; Bourennane, El-Bay; Boutalbi, M.

doi:10.1063/1.2953040

Cited by 1 publication

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“…Usually, in video codec, the local memory is used for recording the coefficients and intermediate data, and the external memory is reserved for recording images of the sequence and the output files. Only for the baseline profile of the codec with I-image and P-image only, which it is possible to use local memory for saving parameters and images [2].…”

Section: A Local and External Memorymentioning

confidence: 99%

“…This great video codec is the latest standard for video coding recommended for any new application. The H.264 encoder combines several efficient algorithms, and the two groups of standarization have paid attention to the concatenation of these algorithms [2]. Indeed, the greatest improvement of H.264 is that the decoder is used in the coding channel [3], in order to manipulate the same images in the encoder as in the decoder at the disadvantage of increased complexity of processing.…”

Section: Introductionmentioning

confidence: 99%

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Memory requirements and simulation platform for the implementation of the H.264 encoder modules

Messaoudi

Bourennane

Toumi

et al. 2010

2010 2nd International Conference on Image Processing Theory, Tools and Applications

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In this paper, we propose a real-time platform for the H.264 CODEC with a memory management method, in which we use a preloading mechanism in order to reduce access to external memory. The platform uses an external DDR2 memory (to record the sequence images) and an intelligent memory controller to read the external memory periodically to load another local memory by the macroblocks (of different sizes) for the processing modules of the H.264 encoder, depending on image manipulation and chosen processing mode. The proposed intelligent controller is tested on a Xilinx virtex5-ML501 platform with multiple internal and external components, including a DDR2 memory. Similarly, the proposed memory controller is well adapted to future System-on-Chip applications with restricted memorybandwidth.

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Section: A Local and External Memorymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%