Property-specific testbench generation for guided simulation

Gupta, A.; Casavant, A.E.; Ashar, P.; Liu, X.G.; Mukaiyama, A.; Wakabayashi, K.

doi:10.1109/aspdac.2002.994973

Cited by 12 publications

(12 citation statements)

References 12 publications

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“…Two markings are consequently valid considering the input and output observed so far. This is reflected in that curmarkings will contain both markings, as shown in Equation (16). (16) The next input comes after 20 time units, when a new token appears in p, this time with the value 5.…”

Section: If the Transition Does Not Results In The Desired Output Thementioning

confidence: 99%

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Model validation for embedded systems using formal method-aided simulation

Karlsson¹,

Eles²,

Peng³

2008

IET Comput. Digit. Tech.

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Section: If the Transition Does Not Results In The Desired Output Thementioning

confidence: 99%

“…Gupta et al [16] apply formal methods to automatically generate a testbench for guided simulation given a model under veri-fication and a CTL property. As a result of their approach, they obtain a testbench which generates stimuli for a subsequent simulation.…”

Section: Introductionmentioning

confidence: 99%

Model validation for embedded systems using formal method-aided simulation

Karlsson¹,

Eles²,

Peng³

2008

IET Comput. Digit. Tech.

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“…The works proposed in [2,14] have combined formal verification techniques with simulation for functional verification. The methodology proposed in [14] extracts an abstract model of the design for the purpose of functional validation.…”

Section: Related Workmentioning

confidence: 99%

Enhancing IP cores specifications using hierarchical composition and set theory

Rodrigues

Silva

Cunha

et al. 2011

Des Autom Embed Syst

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During the functional verification, complex interactions between multiple blocks that compose an Intellectual Property (IP) core can reveal hard-to-find bugs. Functional verification specifications must be precise to assure these interactions occur during the simulation. In this work, we are proposing a technique for improving the functional verification specification of individual blocks, preserving the occurrence of these interaction scenarios in the composition phase. Our approach was implemented for the VeriSC methodology, a SystemC-based functional verification methodology. After each block that composes the IP core was stand-alone verified, we exploit the composition phase using set theory to inThis work was partially funded by the Brazil IP project. 226 C.L. Rodrigues et al.crease the coverage numbers and to justify why some of these numbers cannot, or need not, reach 100%. By applying our approach in a MPEG 4 video decoder design, we show how our work can save functional verification time during the hierarchical composition. Using mutation based-tests, we demonstrate that our work can contribute to error detection. Furthermore, we demonstrate the effectiveness of our approach with regard to traditional structural coverage metrics, such as line coverage and branch coverage.

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“…A typical coverage metric is branch coverage, but there are more code coverage metrics, such as lines, blocks, branches, expressions, paths, and boundary-path. Other techniques (Fallah, 1998); (Gupta, 2002); (Ugarte, 2011) do not depend on the engineer, thus they can be more easily automated. They are also simpler, and provide a first quality metric of the input set.…”

Section: Stimuli Generationmentioning

confidence: 99%