Properties of phosphoric acid doped crystalline silicon with different light-trapping schemes for solar cells

Abdulkadir, Auwal; Alshammari, Aryam Saud

doi:10.1016/j.mssp.2022.107219

Cited by 3 publications

(1 citation statement)

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“…SiNW on the p-type substrate and phosphorus doping for the n-type emitter are the typical reported SiNW solar cells due to the feasibility of the p-type SiNW formation and the cost-effectiveness of the phosphorus sources. H 3 PO 4 [24], P 2 O 5 [25], POCl 3 [26], and commercial spin-on-dopant solution (P-280HP by Desert Silicon) [27] are the reported phosphorus sources for SOD, among which P 2 O 5 is nontoxic and cost-effective.…”

Section: Introductionmentioning

confidence: 99%

Enhancing Si-Nanowire Solar Cell Performance through Fabrication and Annealing Optimization

Muduli,

Kale

2024

Preprint

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The notable optical and electrical features of Si nanowires (SiNWs) outperform conventional bulk silicon, including a large surface area, antireflective properties, and shorter carrier transportation paths for photovoltaics. However, the key challenge lies in the fabrication and doping of SiNWs for p-n junction. The cost-effective metal-assisted chemical etching (MACE) lets the electrolyte etch the rear surface of the substrate. The dot electrode pattern on the front side and the close-periphery electrode on the rear side reduce the photocurrent collection. The spin-on-doping (SOD) leaves phosphorus clusters on the surface during diffusion, which needs dissolution and activation for doping uniformity. The work employs a modified MACE setup to prevent the electrolyte influence on the rear side and increase the photocurrent collection by modifying the front and rear electrode patterns. The increment in the annealing temperature up to 900 ºC dissolves the surface phosphorus clusters and activates the interstitial phosphorus atoms. The optical measurements and Hall mobility confirm the increased active phosphorus atoms. However, the surface oxidation, tip dissolution, and surface defects reduce the power conversion efficiency above the annealing temperature of 900 ºC. Due to increased shunt resistance, the fabrication modification and the annealing temperature optimization improve the power conversion efficiency and FF by 33.7% and 37.6%, respectively.

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Section: Introductionmentioning

confidence: 99%