Properties of generalized Branch and Combine clock networks

El-Amawy, A.; Kulasinghe, P.

doi:10.1109/71.382323

Cited by 3 publications

(8 citation statements)

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“…12 ---4+21ogN a (4) Hence using H-Tree layout, the clocking network has a clock skew of O(vr). [6]. The nodes also are responsible for clocking the data processors or cells (processors hereafter).…”

Section: Tree Clocking Networkmentioning

confidence: 99%

“…In [3] three different networks for clocking a 2-D mesh under BaC principles with varying cost and performance levels have been described. These networks, called F 2, F3, and F 4, are shown in Figures 5,6, and 7, respectively where F x refers to a network employing nodes with Fan-in Fan-out x. Only the F 3 network was analyzed in detail in [ shown that a BaC(n) network can guarantee a constant skew upper bound of (n 1)A, where A is as defined earlier and n is the length of the longest shortest cycle (called feature cycle length) containing any pair of adjacent nodes.…”

Section: Tree Clocking Networkmentioning

confidence: 99%

“…In [12] and [7], algorithms for systematic synthesis of different BaC(n) networks for hypercubes, meshes and tori have been described and proved correct. Interested readers can find more details on BaC clocking in references [3], and [6].…”

Section: Tree Clocking Networkmentioning

confidence: 99%

“…The difference in arrival times is called clock skew. Different aspects of the clock skew problem have been studied in [8], [1], [2]- [6], [13]. The problem clock skew poses is that it directly relates to the clocking rate.…”

mentioning

confidence: 99%

“…The nodes perform simple operations on the clock signals to con, trol skew within known bounds. Clock signal paths are adaptively and automatically selected such that each node is triggered via the shortest delay path from the source to the node [6]. If a pair of communicating data processors or elements are clocked from two nodes which are in the same cycle then the skew is guaranteed to be less than the delay through that cycle.…”

mentioning

confidence: 99%

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A Comparative Study of SynchronousClocking Schemes for VLSI Based Systems

El-Amawy

Maheshwar

1993

VLSI Design

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Recently a novel clock distribution scheme called Branch-and-Combine(BaC) has been proposed. The scheme guarantees constant skew bound irrespective of the size of the clocked network. It utilizes simple nodes to process clock signals such that clock paths are adaptively selected to guarantee constant skew bound. The paper uses a VLSI model to compare the properties of the new scheme to those of the well established H-Tree approach. The H-Tree is a binary tree of simple buffers which is laid out such that leaves are at equal distances from the root. Our study considers clocking 2-D processor meshes of arbitrary sizes. We evaluate and compare the relevant parameters of both schemes in a VLSI layout context. We utilize parameters such as clock skew, link costs, node costs and area efficiency as the basis for comparison. We show that for each BaC network, there is a certain threshold size after which it outperforms the corresponding tree network in terms of skew. We also show that except for node costs, BaC networks outperform the H-Tree, especially when the size of the clocked network is large. As an extension we show that BaC clocking does not suffer from potential pulse disappearance, no matter how large the network is.

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Section: Tree Clocking Networkmentioning

confidence: 99%

Section: Tree Clocking Networkmentioning

confidence: 99%