2014
DOI: 10.4028/www.scientific.net/msf.778-780.649
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Properties of Al Ohmic Contacts to n-type 4H-SiC Employing a Phosphorus-Doped and Crystallized Amorphous-Silicon Interlayer

Abstract: Contact property of aluminum and 4H-SiC wafer with crystallized amorphous-silicon (a-Si) interlayer was investigated. A phosphorus-doped a-Si layer on SiC wafer was crystallized by annealing at 1377 °C. Good ohmic contact behavior and contact resistivity of 2.1 × 10-6Ωcm2were obtained without silicidation annealing process. Furthermore, non-doped crystallized a-Si layer insertion layer also showed ohmic contact property. However, high contact resistivity of 8.2×10-4Ωcm2was obtained in the non-doped a-Si sample… Show more

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Cited by 5 publications
(3 citation statements)
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“…10) It is notable that the reported conduction band discontinuities in Si=SiC heterojunctions fabricated by a conventional bonding method are largely scattered between 0.21 and 1.9 eV. 5,11) This suggests that the electrical properties of the Si=SiC heterojunctions largely vary with surface wet chemical treatment and possible interface states.…”
Section: Introductionmentioning
confidence: 99%
“…10) It is notable that the reported conduction band discontinuities in Si=SiC heterojunctions fabricated by a conventional bonding method are largely scattered between 0.21 and 1.9 eV. 5,11) This suggests that the electrical properties of the Si=SiC heterojunctions largely vary with surface wet chemical treatment and possible interface states.…”
Section: Introductionmentioning
confidence: 99%
“…17 Reported conduction band discontinuities in Si/SiC heterojunctions are largely scattered between 0.21 and 1.9 eV. 7,18 This suggests that the electrical properties of the Si/SiC heterojunctions should be largely varied by the possible interface states. The impact of the interface states to the electrical properties of Si/SiC junctions has not yet been fully understood.…”
mentioning
confidence: 99%
“…The SiC SBD was formed on 10 μm thick n-type (N-dope, 1 × 10 16 cm −3 ) epitaxial layer on 370 μm thick n-type 4H-SiC (4°off, 0.02 Ωcm) wafer. A silicon cap annealing process (SiCA) 26) was performed to form low resistive back contact and Schottky top contacts on the wafer surface. After that, a 150 nm thick SiO 2 layer was deposited for device isolation.…”
mentioning
confidence: 99%