Propagation Characteristics of Multilayer Hybrid Insulator-Metal-Insulator and Metal-Insulator-Metal Plasmonic Waveguides

This article addresses the past, present, and future status of hybrid plasmonic waveguides (HPWs). It presents a comprehensive review of HPW-based photonic integrated circuits (PICs), covering both passive and active devices, as well as potential application of on-chip HPW-based devices. HPW-based integrated circuits (HPWICs) are compatible with complementary metal oxide semiconductor technology, and their matched refractive indices enables the adaptation of existing fabrication processes for silicon-on-insulator designs. HPWs combine plasmonic and photonic waveguide components to provide strong confinement with longer propagation length Lp of HP modes with nominal losses. These HPWs are able to make a trade-off between low loss and longer Lp, which is not possible with independent plasmonic and photonic waveguide components owing to their inability to simultaneously achieve low propagation loss with rapid and effective all-optical functionality. With HPWs, it is possible to overcome challenges such as high Ohmic losses and enhance the functional performance of PICs through the use of multiple discrete components. HPWs have been employed not only to guide transverse magnetic modes but also for optical beam manipulation, wireless optical communication, filtering, computation, sensing of bending, optical signal emission, and splitting. They also have the potential to play a pivotal role in optical communication systems for quantum computing and within data centers. At present, HPW-based PICs are poised to transform wireless chip-to-chip communication, a number of areas of biomedical science, machine learning, and artificial intelligence, as well as enabling the creation of densely integrated circuits and highly compact photonic devices.

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The Design of CMOS-Compatible Plasmonic Waveguides for Intra-Chip Communication

Liu

Cao

et al. 2020

IEEE Photonics J.

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A CMOS-compatible plasmonic waveguide with a metal or metal-like strip sandwiched in-between dielectrics has been proposed for intra-chip communication in the more-than-Moore era. A sequence of numerical models has been presented to evaluate the plasmonic waveguide performance. For device-level consideration, we demonstrated through simulations that Cu (1450 nm pitch) and PLD-TiN (900 nm pitch) plasmonic waveguides symmetrically sandwiched by SiO2 with much smaller and hence denser interconnects, are promising candidates for use in global wires for the asynchronous communication. This design of plasmonic waveguide can bridge the CMOS circuitry and high-speed communication at optical frequencies within chip. For a system-level assessment, both of them have the same bandwidth throughput of ~ 19.8 Gbps. The other performance parameters of Cu and PLD-TiN plasmonic waveguides are respectively, signal latency of ~ 0.18 and 0.19 , energy dissipation per computing bit of ~ 2.5 × 10 −3 fJ/bit and 3.8 × 10 −3 fJ/bit, and 25% crosstalk coupling length of 155 μm and 125 μm. These findings suggest that plasmonic waveguide for intra-chip communication surpass those of existing electronic interconnects for all the categories of performance parameters.

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Propagation Characteristics of Multilayer Hybrid Insulator-Metal-Insulator and Metal-Insulator-Metal Plasmonic Waveguides

Cited by 4 publications

References 21 publications

Deterministic coupling of quantum emitter to surface plasmon polaritons, Purcell enhanced generation of indistinguishable single photons and quantum information processing

Deterministic coupling of quantum emitter to surface plasmon polaritons, Purcell enhanced generation of indistinguishable single photons and quantum information processing

Past, present, and future of hybrid plasmonic waveguides for photonics integrated circuits

The Design of CMOS-Compatible Plasmonic Waveguides for Intra-Chip Communication

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