2016
DOI: 10.1109/led.2016.2544700
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Prolonged 500 °C Demonstration of 4H-SiC JFET ICs With Two-Level Interconnect

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Cited by 52 publications
(52 citation statements)
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“…[24][25][26] Given these promising results, we decided to subject other chips diced from the same prototype IC wafer to electrical testing in simulated Venus surface atmospheric conditions inside the NASA Glenn Extreme Environments Rig (GEER). 27 Ring oscillator chips were selected for the first such test, as these ICs can be operated using the fewest number of wires (one signal output in addition to +V DD , GND, and -V SS chip DC power inputs), are a recognized standard for logic IC demonstration, and provide harmonic output signals that can be detected in frequency spectrum even in the presence of substantial expected electrical noise and output signal path attenuation.…”
mentioning
confidence: 99%
See 1 more Smart Citation
“…[24][25][26] Given these promising results, we decided to subject other chips diced from the same prototype IC wafer to electrical testing in simulated Venus surface atmospheric conditions inside the NASA Glenn Extreme Environments Rig (GEER). 27 Ring oscillator chips were selected for the first such test, as these ICs can be operated using the fewest number of wires (one signal output in addition to +V DD , GND, and -V SS chip DC power inputs), are a recognized standard for logic IC demonstration, and provide harmonic output signals that can be detected in frequency spectrum even in the presence of substantial expected electrical noise and output signal path attenuation.…”
mentioning
confidence: 99%
“…Two NASA Glenn fabricated SiC JFET ring oscillator ICs residing on separate chips were selected for testing in GEER: a 3-stage ring oscillator and an 11-stage ring oscillator that are further described in the supplementary material and elsewhere. [24][25][26]28 Two electrical feedthrough probe assemblies that are further described in the supplementary material were custom-built to enable operational testing of these chips exposed to simulated Venus surface atmosphere in GEER. Each probe assembly nominally provided four outside-chamber electrical connections to the SiC IC chip inside the chamber.…”
mentioning
confidence: 99%
“…This was verified in [45] through demonstration of ICs based on 4H-SiC JFET integrating Hafnium ohmic contact with TaSi 2 interconnect with SiO 2 and SiN 4 dielectric layer hours of stable electrical operation at 500 0 C in the air. The research was extended further by testing the ICs at 727 0 C, after 25 hours of operation little change in electrical properties was noticed due to a quick increase in device resistance [46].…”
Section: Sic Jfet Application In Inverter and Boost Converter Circuitmentioning
confidence: 69%
“…13 From Fig. 6, the capacitor reaches 30 lC/cm 2 above 400 kV/cm, corresponding to read/write voltage of 7.4 V. Such a read/write voltage would be small for the SiC power supply, which is in the range of 10 V to 15 V. [15][16][17] SiC technology at 1 lm could have capacitors with minimum size of 12 lm 2 . Assuming a capacitor over field oxide (COFO) design and relaxed transistor design rules, the minimum amount of memory for a standalone chip (7 mm 9 7 mm) is of the order of 1 Kib to 8 Kib (average areal density 20 b/mm 2 to 160 b/mm 2 ).…”
Section: Room Temperaturementioning
confidence: 99%
“…Digital electronics have been demonstrated to operate up to at least 400°C for complementary metal-oxide-semiconductor (CMOS) field-effect transistors, 15 500°C for junction field-effect transistors (JFETs) 16 and 600°C for emitter coupled logic (ECL, a logic family that uses bipolar junction transistors). 17 Previous efforts to integrate ferroelectrics on SiC include PZT 18,19 and BaSrTiO 3 , 20 with PZT evaluated for HT NVM applications with memory functionality up to 200°C.…”
Section: Introductionmentioning
confidence: 99%