Progress and perspectives in dry processes for nanoscale feature fabrication: fine pattern transfer and high-aspect-ratio feature formation

Abstract

Dramatic advances are being made in dry processing technologies. Atomic scale precision below 10 nm is now possible with fine patterning technologies for high-volume manufacturing of semiconductor devices. The isotropic and anisotropic nature of both film deposition and etching is versatile for nanoscale fabrication of three-dimensional features, such as high-aspect-ratio (HAR) features. Here we conduct a systematic review of the literature over the last 40 years to evaluate the history and progress of dry processes with regard to fine pattern transfer, HAR feature formation, and multiple patterning as lithographic techniques. Finally, we address the major challenges shared across the plasma science and technology community.

Review and future perspective of feature scale profile modeling for high-performance semiconductor devices

“…Kuboi et al 69 , 70 . developed a 3D voxel-slab model for dielectric film (particularly for SiO2 and SiN) etching in which a slab model 10 was coupled with a voxel model to predict both the feature scale profile and damage (dangling bond defects) distribution induced by irradiated ions. In this model, as shown in Fig.…”

“…In the reactive ion etching (RIE) processes, such as atomic layer etching (ALE), 4 – 10 etching processes of the transistors require not only high etching selectivity on the Si fin against mask materials but also low damage on a nanometer scale. As the space between the transistors becomes shorter, verticality of high aspect ratio contact (HARC) etching and high selectivity against the Si substrate is essential considerations.…”

“…Considering deposition processes, 10 – 14 it is important to achieve both good coverage and film properties such as the density, permeability, and adhesion even under the different ARs based on ground materials. Because various types of materials, such as poly-Si, SiO2, SiN, and metals, are stacked with organic films, a deposition process with low temperature ≦100°C is required.…”

Science-based, data-driven developments in plasma processing for material synthesis and device-integration technologies

“…69,70) For the fabrication of wires and interconnects of the device, an insulating film is deposited, and then holes and trenches are manufactured by etching uncovered areas of the film with the protection of a patterned resist mask. 71) Reactive plasma is used for etching the insulating dielectric films, such as silicon dioxide, 72) silicon nitride, 73) silicon oxyfluoride, 74) and silicon oxycarbide. [75][76][77][78] Since the late 1990s, anisotropic etching has been used for the fabrication of deep holes and trenches with dimensions narrower than 100 nm and high-aspect ratios 48) In pulsed plasmas, negative ions can be extracted from the bulk plasma to boundary surface applying electrical reversal potential or positive bias.…”

Novel technology of high-aspect-ratio etch utilizing coverage-controllable atomic layer deposition

“…achieving high selectivity to mask, avoiding etch-stop caused by mask clogging, improving reactive ion etch (RIE)-lag, suppressing bowing critical dimension (CD) and expanding bottom CD. 1,[5][6][7][8][9] For example, the bowing, which is defined as a localized CD expansion of a sidewall on a pattern, is often caused by lateral etch by the bombardment of ion species scattered from the mask. It is necessary to suppress bowing for the shrinkage of the DRAM device since the larger bowing CD decreases the margin between adjacent holes.…”