Programming scheme based optimization of hybrid 4T-2R OxRAM NVSRAM

Abstract

In this paper, we present a novel single-cycle programming scheme for 4T-2R NVSRAM, exploiting pulse engineered input signals. OxRAM devices based on 3 nm thick bi-layer active switching oxide and 90 nm CMOS technology node were used for all simulations. The cell design is implemented for real-time non-volatility rather than last-bit, or power-down nonvolatility. Detailed analysis of the proposed single-cycle, parallel RRAM device programming scheme is presented in comparison to the two-cycle sequential RRAM programming used for similar 4T-2R NVSRAM bit-cells. The proposed single-cycle programming scheme coupled with the 4T-2R architecture leads to several benefits such as-possibility of unconventional transistor sizing, 50% lower latency, 20% improvement in SNM and ∼20× reduced energy requirements, when compared against two-cycle programming approach.

RRAM-based non-volatile SRAM cell architectures for ultra-low-power applications

“…A transmission gate is mainly used to enhance the switching speed, especially in storing "1" as the single NMOS in the traditional 6T SRAM is not able to pass strong "1". The (𝑊 𝐿 ⁄ ) ratio of NMOS and PMOS is kept as the standard minimum with W= 150 nm and L= 130 nm to limit the current during RRAM programming cycles [25]. In the HOLD state, no write or read operation is permitted as the WL is grounded.…”