Programming models and HW-SW interfaces abstraction for multi-processor SoC

Jerraya, Ahmed; Bouchhima, A.; Pétrot, Frédéric

doi:10.1145/1146909.1146981

Cited by 52 publications

(24 citation statements)

References 13 publications

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“…Jerraya et al [5] discuss a design methodology based on a hardware/software layered interface and suggest a three-layered interface. This interface includes the parallel programming model, hardware dependent software, and hardware abstraction layer.…”

Section: B Related Workmentioning

confidence: 99%

Systematic integration of flowgraph- and module-level parallelism in implementation of DSP applications on multiprocessor systems-on-chip

Zhou

Shen

Plishker

et al. 2012

2012 IEEE 11th International Conference on Signal Processing

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Abstract-Increasing use of multiprocessor system-on-chip (MPSoC) technology is an important trend in the design and implementation of signal processing systems. However, the design of efficient DSP software for MPSoC platforms involves complex inter-related steps, including data decomposition, memory management, and inter-task and inter-thread synchronization. These design steps are challenging, especially under strict constraints on performance and power consumption, and tight time to market pressures. To facilitate these steps, we have developed a new dataflow based design flow within the targeted dataflow interchange format (TDIF) design tool. Our new MPSoC-oriented design flow, called TDIF-PPG, is geared towards analysis and mapping of embedded DSP applications on MPSoCs. An important feature of TDIF-PPG is its capability to integrate graph level parallelism for DSP system flowgraphs and actor level parallelism for DSP functional modules into the application mapping processing. Here, graph level parallelism is exposed by the dataflow graph application representation in TDIF, and actor level parallelism is modeled by a novel model for multiprocessor dataflow graph implementation that we call the parallel processing group (PPG) model. We demonstrate our approach through actor and subsystem design for software defined radio.

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Section: B Related Workmentioning

confidence: 99%

Systematic integration of flowgraph- and module-level parallelism in implementation of DSP applications on multiprocessor systems-on-chip

Zhou

Shen

Plishker

et al. 2012

2012 IEEE 11th International Conference on Signal Processing

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“…In our work, we face a complete HW-SW co-design complementing previous works [10,24,26] designing explicitly the interface between hardware and software components, and extending them, in the sense that we are going further by exposing the QoS support on top of an OpenMP parallel programming model, and the runtime library specially targeted to NoC-based MPSoC platforms.…”

Section: Related Workmentioning

confidence: 99%

Exploring programming model-driven QoS support for NoC-based platforms

Joven

Marongiu

Angiolini³

et al. 2010

Proceedings of the Eighth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

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Networks-on-Chip (NoCs) are being increasingly considered as a central enabling technology to communication-centric designs as more and more IP blocks are integrated on the same SoC. Embedded applications, in turn, are becoming extremely sophisticated, and often require guaranteed levels of service and performance. The complex and non-uniform nature of network traffic generated by parallel applications running on a large number of possibly heterogeneous IPs makes a strong case for providing Quality of Service (QoS) support for traffic streams over the NoC infrastructure.In this paper we consider an integrated hardware/software approach for delivering QoS at the application level. We designed NoC hardware support, low-level middleware and APIs which enable QoS control at the application level. Furthermore, we identify a set of programming abstractions useful to associate the notion of priority to each running task in the system. An initial implementation of this programming model is also presented, which leverages a set of extensions to a MPSoC-specific OpenMP compiler and runtime environment.

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“…Work focusing on the mapping of applications onto MP-SoCs, in the form of programming models, can be found in, e.g., [14,6].…”

Section: Related Workmentioning

confidence: 99%

A framework for rapid system-level exploration, synthesis, and programming of multimedia MP-SoCs

Thompson

Nikolov

Stefanov

et al. 2007

Proceedings of the 5th IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis

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In this paper, we present the Daedalus framework, which allows for traversing the path from sequential application specification to a working MP-SoC prototype in FPGA technology with the (parallelized) application mapped onto it in only a matter of hours. During this traversal, which offers a high degree of automation, guidance is provided by Daedalus' integrated system-level design space exploration environment. We show that Daedalus offers remarkable potentials for quickly experimenting with different MP-SoC architectures and exploring system-level design options during the very early stages of design. Using a case study with a Motion-JPEG encoder application, we illustrate Daedalus' design steps and demonstrate its efficiency.

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Programming models and HW-SW interfaces abstraction for multi-processor SoC

Cited by 52 publications

References 13 publications

Systematic integration of flowgraph- and module-level parallelism in implementation of DSP applications on multiprocessor systems-on-chip

Systematic integration of flowgraph- and module-level parallelism in implementation of DSP applications on multiprocessor systems-on-chip

Exploring programming model-driven QoS support for NoC-based platforms

A framework for rapid system-level exploration, synthesis, and programming of multimedia MP-SoCs

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