Programming model for a heterogeneous x86 platform

SahaBratin,; ZhouXiaocheng,; ChenHu,; GaoYing,; YanShoumeng,; RajagopalanMohan,; FangJesse,; ZhangPeinan,; RonenRonny,; MendelsonAvi,

doi:10.1145/1543135.1542525

Cited by 17 publications

(12 citation statements)

References 12 publications

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“…Such a hardware has allowed GPU-based applications to run over 400x faster than equivalent CPU based programs [1]. This trend is likely to continue, as upcoming hardware more closely integrates GPUs and CPUs [2], and new models of heterogeneous hardware are introduced [3].…”

Section: Introductionmentioning

confidence: 99%

Performance Debugging of GPGPU Applications with the Divergence Map

Coutinho

Sampaio

Pereira

et al. 2010

2010 22nd International Symposium on Computer Architecture and High Performance Computing

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The increasing programability and the high computational power of Graphical Processing Units (GPU) make them attractive to general purpose programming. However, taking full benefit of this execution environment is a challenging task. One of these challenges stem from divergences, a phenomenon that occurs when threads that execute in lock-step are forced to take different program paths due to branches in the code. In face of divergences, some threads will have to wait, idly, while their diverging siblings execute. Optimizing the code to avoid divergences is difficult, because this task demands a deep understanding of programs that might be large and convoluted. In order to facilitate the detection of divergences, this paper introduces the divergence map, a data structure that indicates the location and the volume of divergences in a program. We build this map via dynamic profiling techniques, which we have implemented on top of an open source CUDA compiler. To illustrate the importance of the divergence map, we have used it to pin-point the core regions that must be optimized in well known public applications. By hand optimizing some applications, we have added 9-11% speedups onto kernels that have already gone through the sieve of many programmers.

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Section: Introductionmentioning

confidence: 99%

Performance Debugging of GPGPU Applications with the Divergence Map

Coutinho

Sampaio

Pereira

et al. 2010

2010 22nd International Symposium on Computer Architecture and High Performance Computing

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“…The two primary approaches to keeping memory coherent between the PUs: distributed shared memory (such as, Intel's MYO [50] and GMAC [51]) and message passing-like models (such as CUDA's explicit memory copy calls and Intel MIC's offload model). The current implementation of AHP uses explicit data transfer calls to maintain memory consistency based on the DAG consistency model.…”

Section: F Final Code Generationmentioning

confidence: 99%

Automatic generation of software pipelines for heterogeneous parallel systems

Pienaar¹,

Chakradhar²,

Raghunathan³

2012

2012 International Conference for High Performance Computing, Networking, Storage and Analysis

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Pipelining is a well-known approach to increasing parallelism and performance. We address the problem of software pipelining for heterogeneous parallel platforms that consist of different multi-core and many-core processing units. In this context, pipelining involves two key steps-partitioning an application into stages and mapping and scheduling the stages onto the processing units of the heterogeneous platform. We show that the inter-dependency between these steps is a critical challenge that must be addressed in order to achieve high performance. We propose an Automatic Heterogeneous Pipelining framework (AHP) that generates an optimized pipelined implementation of a program from an annotated unpipelined specification. Across three complex applications (image classification, object detection, and document retrieval) and two heterogeneous platforms (Intel Xeon multi-core CPUs with Intel MIC and NVIDIA GPGPU accelerators), AHP achieves a throughput improvement of up to 1.53x (1.37x on average) over a heterogeneous baseline that exploits data and task parallelism.

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“…There are some new parallel programming models [3,31,33,38] proposed for heterogeneous multicore architectures. Even though OpenCL inherited many features from CUDA [31], their approaches are significantly different.…”

Section: Related Workmentioning

confidence: 99%

“…CUDA [31] and CTM [3] are programming models that are specific to a system that consists of CPUs and GPUs. Saha et al [33] propose a programming model for a heterogeneous x86 platform. The target architecture consists of a general-purpose x86 CPU and Larrabee cores [34].…”

Section: Related Workmentioning

confidence: 99%

An OpenCL framework for heterogeneous multicores with local memory

Lee

Kim

Seo

et al. 2010

Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques

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In this paper, we present the design and implementation of an Open Computing Language (OpenCL) framework that targets heterogeneous accelerator multicore architectures with local memory. The architecture consists of a general-purpose processor core and multiple accelerator cores that typically do not have any cache. Each accelerator core, instead, has a small internal local memory. Our OpenCL runtime is based on software-managed caches and coherence protocols that guarantee OpenCL memory consistency to overcome the limited size of the local memory. To boost performance, the runtime relies on three source-code transformation techniques, work-item coalescing, web-based variable expansion and preload-poststore buffering, performed by our OpenCL C source-to-source translator. Work-item coalescing is a procedure to serialize multiple SPMD-like tasks that execute concurrently in the presence of barriers and to sequentially run them on a single accelerator core. It requires the webbased variable expansion technique to allocate local memory for private variables. Preload-poststore buffering is a buffering technique that eliminates the overhead of software cache accesses. Together with work-item coalescing, it has a synergistic effect on boosting performance. We show the effectiveness of our OpenCL framework, evaluating its performance with a system that consists of two Cell BE processors. The experimental result shows that our approach is promising.

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Programming model for a heterogeneous x86 platform

Cited by 17 publications

References 12 publications

Performance Debugging of GPGPU Applications with the Divergence Map

Performance Debugging of GPGPU Applications with the Divergence Map

Automatic generation of software pipelines for heterogeneous parallel systems

An OpenCL framework for heterogeneous multicores with local memory

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