Programming Abstractions for Preemptive Scheduling on FPGAs Using Partial Reconfiguration

Rodriguez-Canal, Gabriel; Brown, Nick; Torres, Yuri; González-Escribano, Arturo

doi:10.1007/978-3-031-31209-0_10

Cited by 1 publication

(3 citation statements)

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“…This work extends a previous prototype presented in Reference 8, in how we serve the tasks and the synchronization mechanisms. Furthermore, we have also decoupled our two techniques for DPR and kernel interruption/resumption, allowing for preemption when using full FPGA reconfiguration.…”

Section: Introductionmentioning

confidence: 62%

“…Therefore, as long as there are enough tasks in the queue, the reconfigurable regions will be assigned tasks. This was not ensured in the previous version of the scheduler that was presented in Reference 8 which, although it kept the regions at full occupation in many scenarios, was not guaranteed for all mixes of tasks. Finally, line 17 updates the timeout for the next arriving task.…”

Section: Approach To Support Preemptive Scheduling On Fpgasmentioning

confidence: 99%

“…The scheduler presented in Reference 8 was extended to support the preemption of tasks using full reconfiguration. Under this full reconfiguration regime the entire FPGA is halted until reconfiguration has completed, and therefore the state of running tasks must be saved in advance.…”

Section: Approach To Support Preemptive Scheduling On Fpgasmentioning

confidence: 99%

See 2 more Smart Citations

Task‐based preemptive scheduling on FPGAs leveraging partial reconfiguration

Rodriguez-Canal

Brown

Torres

et al. 2023

Concurrency and Computation

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SummaryField‐programmable gate arrays (FPGAs) are an attractive type of accelerator for all‐purpose high performance computing computing systems due to the possibility of deploying tailored hardware on demand. However, the common tools for programming and operating FPGAs are still complex to use, especially in scenarios where diverse types of tasks should be dynamically executed. In this work, we present a programming abstraction with a simple interface that internally leverages high‐level synthesis, dynamic partial reconfiguration and synchronization mechanisms to use an FPGA as a multi‐tasking server with preemptive scheduling and priority queues. This leads to an improved use of the FPGA resources, allowing the execution of several different kernels concurrently and deploying the most urgent ones as fast as possible. The results of our experimental study show that our approach incurs only a 10 5% overhead in the worst case when using two reconfigurable regions, whilst providing a significant performance improvement of at least 24 21% over the traditional full reconfiguration approach.

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Section: Introductionmentioning

confidence: 62%

Section: Approach To Support Preemptive Scheduling On Fpgasmentioning

confidence: 99%