Programmable Low-Power Multicore Coprocessor Architecture for HEVC/H.265 In-Loop Filtering

Hautala, Ilkka; Boutellier, Jani; Hannuksela, Jari; Silvén, Olli

doi:10.1109/tcsvt.2014.2369744

Cited by 13 publications

(9 citation statements)

References 23 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…These filters are the deblocking filter (DF) [35] and the sample adaptive offset filter (SAO) [36]. The dataflow description of the inloop filters is based on the authors' prior work [37], and it consists of five actors in the simplest case, where only one tile is used. As shown in Fig.…”

Section: Hevc Inloop Filteringmentioning

confidence: 99%

“…The actor network processes the video in a coding tree block (CTB) basis, and the token sizes of FIFOs are selected based on the size of the CTB. In the case of a 64 × 64 CTB, the token size is about 5 kB depending on the needed coding parameters, which are explained in detail in [37]. The HEVC Inloop Filtering application uses TTA special function units, which is not the case for the other test applications.…”

Section: Hevc Inloop Filteringmentioning

confidence: 99%

“…The first category of coprocessing systems is referred to as Inloop, and consists of TTA cores tailored for HEVC Inloop filtering. This core type is presented in detail in [37] 2 . In the second category, referred to as Shared, the co-processing system is based on one of the predefined TTA core architectures from [23], where it is called custom 2 .…”

Section: Tta Co-processing System Architecturesmentioning

confidence: 99%

See 2 more Smart Citations

TTADF: Power Efficient Dataflow-Based Multicore Co-Design Flow

Hautala

Boutellier

Silvén

2020

IEEE Trans. Comput.

Self Cite

View full text Add to dashboard Cite

The era of mobile communications and the Internet of Things (IoT) has introduced numerous challenges for mobile processing platforms that are responsible for increasingly complex signal processing tasks from different application domains. In recent years, the power efficiency of computing has been improved by adding more parallelism and workload-specific computing resources to such platforms. However, programming of parallel systems can be time-consuming and challenging if only low-level programming methods are used. This work presents a dataflow-based co-design framework TTADF that reduces the design effort of both software and hardware design for mobile processing platforms. The paper presents three application examples from the fields of video coding, machine vision, and wireless communications. The application examples are mapped and profiled both on a pipelined and a shared-memory multicore platform that is generated by TTADF. The results of the TTADF co-design-based solutions are compared against previous manually created designs and a recent dataflow-based design flow, showing that TTADF provides very high energy efficiency together with a high level of automation in software and hardware design.

show abstract

Section: Hevc Inloop Filteringmentioning

confidence: 99%

Section: Hevc Inloop Filteringmentioning

confidence: 99%

Section: Tta Co-processing System Architecturesmentioning

confidence: 99%

See 1 more Smart Citation

TTADF: Power Efficient Dataflow-Based Multicore Co-Design Flow

Hautala

Boutellier

Silvén

2020

IEEE Trans. Comput.

Self Cite

View full text Add to dashboard Cite

show abstract

“…In few architectures, the novel filter ordering is proposed to improve the performance. Different architectures are implemented in [5,7,8,9,10,11,12,13,14] to realize the deblocking filter of H.265 coding standard in hardware. It is seen that the complexity of H.265 deblocking filter architecture is less compared to the H.264 deblocking filter architecture [15].…”

Section: Related Workmentioning

confidence: 99%

Five-stage pipelined dual-edge deblocking filter architecture for H.265 video codec

Christopher

Sivanantham

2019

IEICE Electron. Express

View full text Add to dashboard Cite

High-Efficiency Video Coding (HEVC/H.265) is the latest video coding standard used in various applications. In HEVC, the quality of the reconstructed video is enhanced by two in-loop filters (Deblocking filter and Sample Adaptive Offset filter). In this paper, we propose an efficient resource sharing hardware architecture for deblocking filter. This architecture utilizes four edge filters to filter two edges of the 8 × 8 block in parallel. The edges are filtered following the sequential filter ordering. The proposed architecture is implemented in Verilog HDL and synthesized using Synopsys DC. The simulation results show that this architecture can process a 16 × 16 block in 45 clock cycles and hence an LCU in 720 clock cycles. It utilizes an area of 93.5 K in 32 nm technology supporting UHD video which is suitable for real-time applications.

show abstract

“…In [17], the authors decreased the frame-level parallelism for the SAO procedure by including it in the CTU decoding procedure, in order to better exploit memory-bandwidth and cache performance. A similar design is proposed in [3] (for CPUs) and in [9], which presents a very low-power programmable coprocessor architecture targeting especially embedded devices.…”

Section: Related Workmentioning

confidence: 99%

GPU Parallelization of HEVC In-Loop Filters

Wang

Souza

Alvarez-Mesa

et al. 2017

Int J Parallel Prog

View full text Add to dashboard Cite

bstract In the High Efficiency Video Coding (HEVC) standard, multiple decoding modules have been designed to take advantage of parallel processing. In particular, the HEVC in-loop filters (i.e., the deblocking filter and sample adaptive offset) were conceived to be exploited by parallel architectures. However, the type of the offered parallelism mostly suits the capabilities of multi-core CPUs, thus making a real challenge to efficiently exploit massively parallel architectures such as Graphic Processing Units (GPUs), mainly due to the existing data dependencies between the HEVC decoding procedures. In accordance, this paper presents a novel strategy to increase the amount of parallelism and the resulting performance of the HEVC inloop filters on GPU devices. For this purpose, the proposed algorithm performs the HEVC filtering at frame-level and employs intrinsic GPU vector instructions. When compared to the state-of-the-art HEVC in-loop filter implementations, the proposed approach also reduces the amount of required memory transfers, thus further boosting the performance. Experimental results show that the proposed GPU in-loop filters deliver a significant improvement in decoding performance. For example, average frame rates of 76 frames per second (FPS) and 125 FPS for Ultra HD 4K are achieved on an embedded NVIDIA GPU for All Intra and Random Access configurations, respectively.

show abstract

Programmable Low-Power Multicore Coprocessor Architecture for HEVC/H.265 In-Loop Filtering

Cited by 13 publications

References 23 publications

TTADF: Power Efficient Dataflow-Based Multicore Co-Design Flow

TTADF: Power Efficient Dataflow-Based Multicore Co-Design Flow

Five-stage pipelined dual-edge deblocking filter architecture for H.265 video codec

GPU Parallelization of HEVC In-Loop Filters

Contact Info

Product

Resources

About