Programmable logic using a SET electron box

Klunder, R.H.; Hoekstra, Jaap

doi:10.1109/icecs.2001.957711

Cited by 15 publications

(10 citation statements)

References 3 publications

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“…Klunder and Hoekstra [188] have proposed the use of the electron box as a programmable logic circuit (NAND and NOR functions) and, although not explicitly mentioned, arbitrary TLGs. It consists of an electron box [see Fig.…”

Section: A Single Electron Tunneling (Set) Solutionsmentioning

confidence: 99%

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VLSI implementations of threshold logic- a comprehensive survey

Beiu

Quintana

Avedillo

2003

IEEE Trans. Neural Netw.

193

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This paper is an in-depth review on silicon implementations of threshold logic gates that covers several decades. In this paper, we will mention early MOS threshold logic solutions and detail numerous very-large-scale integration (VLSI) implementations including capacitive (switched capacitor and floating gate with their variations), conductance/current (pseudo-nMOS and output-wired-inverters, including a plethora of solutions evolved from them), as well as many differential solutions. At the end, we will briefly mention other implementations, e.g., based on negative resistance devices and on single electron technologies.

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Section: A Single Electron Tunneling (Set) Solutionsmentioning

confidence: 99%

“…The RTD is a two-terminal device without input-output capabilities. A specific logic functionality of a MOBILE is determined by [187] and (b) programmable gate from [188], and (c) n-input TLG from [189].…”

Section: B Resonant Tunneling Devices (Rtds)mentioning

confidence: 99%

VLSI implementations of threshold logic- a comprehensive survey

Beiu

Quintana

Avedillo

2003

IEEE Trans. Neural Netw.

193

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“…With appropriate configuration a simple SET circuit can function as NAND logic, as shown in Fig. 9 [16]. The SET NAND gate consists of a single tunnel junction and one capacitor as well as two input capacitors.…”

Section: Applicationmentioning

confidence: 99%

A system architecture solution for unreliable nanoelectronic devices

Han

Jonker

2002

IEEE Trans. Nanotechnology

162

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Abstract-Due to the manufacturing process, the shrinking of electronic devices will inevitably introduce a growing number of defects and even make these devices more sensitive to external influences. It is, therefore, likely that the emerging nanometer-scale devices will eventually suffer from more errors than classical silicon devices in large scale integrated circuits. In order to make systems based on nanometer-scale devices reliable, the design of fault-tolerant architectures will be necessary. Initiated by von Neumann, the NAND multiplexing technique, based on a massive duplication of imperfect devices and randomized imperfect interconnects, had been studied in the past using an extreme high degree of redundancy. In this paper, this NAND multiplexing is extended to a rather low degree of redundancy, and the stochastic Markov nature in the heart of the system is discovered and studied, leading to a comprehensive fault-tolerant theory. A system architecture based on NAND multiplexing is investigated by studying the problem of the random background charges in single electron tunneling (SET) circuits. Our evaluation shows that it might be a system solution for an ultra large integration of highly unreliable nanometer-scale devices.

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“…Some of the most used SENDs are the Single Electron Box (SEB), the SE Linear Threshold Gate (LTG), and the Single Electron Transistor (SET) [5][6][7][8]. The design of different SE logic gates are reported in [9][10][11][12].…”

Section: Introductionmentioning

confidence: 99%

D3. Design and simulation of novel single-electron coding nano-circuits using room temperature summing-inverter gates

Yakout

Rehan

2012

2012 29th National Radio Science Conference (NRSC)

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The Single-Electron (SE) summing-inverter (SI) NOR and NAND gates are among the basic functional SE circuits. In this paper, the design of multi-input SE SI NOR and NAND gates are reviewed. Novel SE decimal-to-BCD encoders and binary decoders, which are composed of SI gates, are designed for all combinations of active inputs and outputs. The simulated designs work properly with only one voltage source of 500 mV for a wide range of temperatures (from 40K to 400K). The detailed schematic diagrams along with the corresponding SIMON 2 simulation results at room temperature (that include input and output signals as well as the stability diagrams) of the novel SE decimal-to-BCD encoders as well as the developed SE binary decoders are presented.

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Programmable logic using a SET electron box

Cited by 15 publications

References 3 publications

VLSI implementations of threshold logic- a comprehensive survey

VLSI implementations of threshold logic- a comprehensive survey

A system architecture solution for unreliable nanoelectronic devices

D3. Design and simulation of novel single-electron coding nano-circuits using room temperature summing-inverter gates

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