Programmable analogue circuits with multilevel memristive device

Park, S.; Park, J.; Kim, S.; Lee, W.; Lee, B.H.; Hwang, Hyunsang

doi:10.1049/el.2012.3179

Cited by 2 publications

(3 citation statements)

References 12 publications

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“…So vertex 4 is also combined with vertex 2. On the other hand, the CA cells whose value changed from '1' to '0' have coordinates (4,8), (5, 0) and (3,0). Similarly, here the vertex which participates more is vertex 0, which however is already combined with vertex 5 from the previous case, so no further action is needed.…”

Section: Simulation Resultsmentioning

confidence: 99%

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Memristive Computing for NP-Hard AI Problems

Vourkas

Sirakoulis

2015

Emergence, Complexity and Computation

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The memristor has definitely shown abilities that could revolutionize computing in the coming decades [1][2][3][4]. Its unique adaptive properties are ideal for computational purposes and, so far, they have motivated the exploration of novel computing paradigms [5][6][7]. The pinched current-voltage hysteresis feature indicates the potential of using it in a continuous operational mode as part of an analog computational paradigm [8][9][10][11]. For example, reported properties of network configurations of memristors, as presented in Chap. 7, showed that composite memristive systems significantly improve the efficiency of logic operations via massive analog parallelism, where calculation consists in the evolution of the memristance of all the involved devices. Massive parallelism is commonly found in nature, hence massively parallel computing systems and architectures constitute a great technological engineering challenge [12][13][14].However, in Chap. 7 we extensively discussed the major disadvantages and the computing inefficiencies of memristive networks which are mostly attributed to the dependence of the computing medium behavior on the symmetry of both the underlying circuit geometry and the employed devices. Such inefficiencies were properly treated with the inclusion of asymmetries in the computing structure through a variety of composite memristive components [15][16][17]. Nevertheless, this necessary range of electronic components available so that the requirements of different application are met, reduces significantly the overall structural homogeneity and simplicity of the hardware (HW). Moreover, among the mentioned drawbacks we distinguish: (i) the need to access all the memristors sequentially, both for their initialization and for the read-out of the network state; (ii) the power consumption (the minimum necessary applied input voltage normally varies). It was mentioned, though, that the sparse nature of such memristor network-based computations resembles certain operational features and computing capabilities of

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Section: Simulation Resultsmentioning

confidence: 99%

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confidence: 99%

Memristive Computing for NP-Hard AI Problems

Vourkas

Sirakoulis

2015

Emergence, Complexity and Computation

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“…Sorting networks, which use comparators built of a series of reciprocally placed memristors, were previously studied in [2]. Memristors (concatenation of 'memory resistors') constitute a recently discovered class of two-terminal passive non-volatile resistance-switching devices which have so far shown abilities that could revolutionise hardware (HW) computing architectures [3][4][5][6][7]. However, the aforementioned network-based HW approach has the following disadvantages, which render its practical use questionable: (i) the comparators' output levels gradually degrade through cascading, thus signal rectification is occasionally required and (ii) the complexity of interconnections increases significantly as the size of the problem (the number of inputs) increases.…”

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Memristor‐based parallel sorting approach using one‐dimensional cellular automata

Vourkas

Stathis

2014

Electron. lett.

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A novel memristor-based circuit-level cellular automata (CA)-inspired approach to the solution of the classic sorting problem of n Keys in a linear array is presented. The presented system utilises the structural simplicity of CA combined with the threshold-type switching behaviour of memristors and composite memristive components; the latter is used for both information encoding and computation. The focus is on a threshold-type model for memristors for the implementation of the fundamental CA cell and the overall CA operation is verified via simulations.Introduction: Since the dawn of computing, the sorting problem has been one of the most extensively researched subjects [1]. The main purpose of sorting information is to optimise its usefulness for specific tasks that require sorted input data. Sorting networks, which use comparators built of a series of reciprocally placed memristors, were previously studied in [2]. Memristors (concatenation of 'memory resistors') constitute a recently discovered class of two-terminal passive non-volatile resistance-switching devices which have so far shown abilities that could revolutionise hardware (HW) computing architectures [3][4][5][6][7]. However, the aforementioned network-based HW approach has the following disadvantages, which render its practical use questionable: (i) the comparators' output levels gradually degrade through cascading, thus signal rectification is occasionally required and (ii) the complexity of interconnections increases significantly as the size of the problem (the number of inputs) increases.This Letter addresses the classic sorting problem of n values (Keys) in a linear array by proposing a novel memristor-based circuit-level parallel approach inspired by one-dimensional (1D) cellular automata (CA) [8]. CA constitute a well-studied, inherently parallel, efficient and robust computing paradigm [9]. Owing to their ability to capture globally emerging behaviour from the local collective interaction of simple components, CA have been successfully applied to several computational problems [8][9][10]. Indeed, when CA-based algorithms are implemented in HW they are executed fast by exploiting the parallel structure of CA; HW design reduces to the design of a single CA cell, whereas the overall layout results regular with local interconnections. Here, we present the design of the fundamental memristive CA cell that implements the CA update rule which we employed in the creation of a 1D computational structure, which executes parallel sorting of input Keys. Within the cells, information is encoded in the resistive states of threshold-type switching memristors and composite memristive components. Compared with [2], the proposed design combines the computational capabilities and the size-independent simple structure of CA with the unique circuit properties of memristors, to provide a HW capable of executing computations within memory:

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Programmable analogue circuits with multilevel memristive device

Cited by 2 publications

References 12 publications

Memristive Computing for NP-Hard AI Problems

Memristive Computing for NP-Hard AI Problems

Memristor‐based parallel sorting approach using one‐dimensional cellular automata

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