Programmable 28nm coprocessor for HEVC/H.265 in-loop filters

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

Silvén

2018

Self Cite

An application specific programmable processor is designed based on the analysis of a set of greedy recovery Compressive Sensing (CS) algorithms. The solution is flexible and customizable for a wide range of problem dimensions, as well as algorithms. The versatility of the approach is demonstrated by implementing Orthogonal Matching Pursuits, Approximate Messaging Passing and Normalized Iterative Hard Thresholding algorithms, all using a high-level language. Transported Triggered Architecture (TTA) framework is employed for the efficient implementation of macro operations shared by the algorithms. The performance of the CS algorithms on ARM Cortex-A15 and NIOS II processors has also been investigated, and empirical comparisons are presented. The flexible hardware design implemented on an FPGA achieves up to 7.80Ksample/s recovery at a power dissipation of 42μJ/sample and beats both ARM and NIOS in total power consumption.

Section: Resultsmentioning

confidence: 99%

An Embedded Programmable Processor for Compressive Sensing Applications

Safarpour

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

Silvén

2018

Self Cite

“…The size of memory blocks has been minimized for keeping on-chip SRAM size realistic and for improving power efficiency. The authors of this paper have already shown in [40] that the power consumption of a TTA co-processing system such as Inloop3 is between 66 mW and 207 mW when the clock frequency is ranges between 530 MHz and 1.2 GHz.…”

Section: Tta Co-processing System Architecturesmentioning

confidence: 91%

“…Inloop3, presented in Fig. 11, is a special case, and it is initially tailored for HEVC Inloop filtering [40]. The TTA cores are connected using shared SRAM memories so that a three-stage pipeline is formed.…”

Section: Tta Co-processing System Architecturesmentioning

confidence: 99%

“…follows a ring topology, where data can be moved into both directions. In [40], the authors show that the Inloop TTA coprocessing system can achieve a 1.2 GHz clock frequency (1.0 V operating voltage) when placed and routed using 28 nm standard cell technology. Based on that result, in the experiments, a clock frequency of 1.2 GHz is assumed in all Inloop system configurations.…”

Section: Tta Co-processing System Architecturesmentioning

confidence: 99%

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TTADF: Power Efficient Dataflow-Based Multicore Co-Design Flow

Boutellier

Silvén

2020

IEEE Trans. Comput.

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The era of mobile communications and the Internet of Things (IoT) has introduced numerous challenges for mobile processing platforms that are responsible for increasingly complex signal processing tasks from different application domains. In recent years, the power efficiency of computing has been improved by adding more parallelism and workload-specific computing resources to such platforms. However, programming of parallel systems can be time-consuming and challenging if only low-level programming methods are used. This work presents a dataflow-based co-design framework TTADF that reduces the design effort of both software and hardware design for mobile processing platforms. The paper presents three application examples from the fields of video coding, machine vision, and wireless communications. The application examples are mapped and profiled both on a pipelined and a shared-memory multicore platform that is generated by TTADF. The results of the TTADF co-design-based solutions are compared against previous manually created designs and a recent dataflow-based design flow, showing that TTADF provides very high energy efficiency together with a high level of automation in software and hardware design.

“…Ijzerman et al [12] proposed programmable SIMD TTA-based accelerator for convolutional neural networks. Also, in [11] a coarse-grained multi-core TTA was designed for video coding applications.…”

Section: Introductionmentioning

confidence: 99%

Transport Triggered Array Processor for Vision Applications

Safarpour

Lecture Notes in Computer Science

López

et al. 2019

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Low-level sensory data processing in many Internet-of-Things (IoT) devices pursue energy efficiency by utilizing sleep modes or slowing the clocking to the minimum. To curb the share of stand-by power dissipation in those designs, near-threshold/sub-threshold operational points or ultra-low-leakage processes in fabrication are employed. Those limit the clocking rates significantly, reducing the computing throughputs of individual processing cores. In this contribution we explore compensating for the performance loss of operating in near-threshold region (Vdd =0.6V) through massive parallelization. Benefits of near-threshold operation and massive parallelism are optimum energy consumption per instruction operation and minimized memory roundtrips, respectively. The Processing Elements (PE) of the design are based on Transport Triggered Architecture. The fine grained programmable parallel solution allows for fast and efficient computation of learnable low-level features (e.g. local binary descriptors and convolutions). Other operations, including Max-pooling have also been implemented. The programmable design achieves excellent energy efficiency for Local Binary Patterns computations.