ProfileMe: hardware support for instruction-level profiling on out-of-order processors

Dean, Jeffrey A.; Hicks, James E.; Waldspurger, Carl A.; Weihl, William E.; Chrysos, George

doi:10.1109/micro.1997.645821

Cited by 145 publications

(122 citation statements)

References 12 publications

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“…Using this approach, a performancemonitoring tool, such as ProfileMe [5] or DCPI [1], could randomly elect to measure performance characteristics of individual instructions as they flowed through the processor pipeline. The tool could, then, gather this information over the execution of an application and attribute performance problems to certain instructions statistically.…”

Section: Microprocessor Hardware Performance Countersmentioning

confidence: 99%

Scalable Analysis Techniques for Microprocessor Performance Counter Metrics

Ahn¹,

Vetter²

2002

ACM/IEEE SC 2002 Conference (SC'02)

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Contemporary microprocessors provide a rich set of integrated performance counters that allow application developers and system architects alike the opportunity to gather important information about workload behaviors. Current techniques for analyzing data produced from these counters use raw counts, ratios, and visualization techniques help users make decisions about their application performance. While these techniques are appropriate for analyzing data from one process, they do not scale easily to new levels demanded by contemporary computing systems. Very simply, this paper addresses these concerns by evaluating several multivariate statistical techniques on these datasets. We find that several techniques, such as statistical clustering, can automatically extract important features from the data. These derived results can, in turn, be fed directly back to an application developer, or used as input to a more comprehensive performance analysis environment, such as a visualization or an expert system.

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Section: Microprocessor Hardware Performance Countersmentioning

confidence: 99%

Scalable Analysis Techniques for Microprocessor Performance Counter Metrics

Ahn¹,

Vetter²

2002

ACM/IEEE SC 2002 Conference (SC'02)

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“…Dean et al [15] developed the first instruction sampling techniques in their ProfileMe framework for the DEC Alpha processors. This was the precursor to modern instruction sampling techniques only now appearing in Intel and AMD chips as PEBS and IBS, respectively [4].…”

Section: A Memory Instruction Measurementmentioning

confidence: 99%

Dissecting On-Node Memory Access Performance: A Semantic Approach

Giménez

Gamblin

Rountree

et al. 2014

SC14: International Conference for High Performance Computing, Networking, Storage and Analysis

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Abstract-Optimizing memory access is critical for performance and power efficiency. CPU manufacturers have developed sampling-based performance measurement units (PMUs) that report precise costs of memory accesses at specific addresses. However, this data is too low-level to be meaningfully interpreted and contains an excessive amount of irrelevant or uninteresting information.We have developed a method to gather fine-grained memory access performance data for specific data objects and regions of code with low overhead and attribute semantic information to the sampled memory accesses. This information provides the context necessary to more effectively interpret the data. We have developed a tool that performs this sampling and attribution and used the tool to discover and diagnose performance problems in real-world applications. Our techniques provide useful insight into the memory behavior of applications and allow programmers to understand the performance ramifications of key design decisions: domain decomposition, multi-threading, and data motion within distributed memory systems.

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“…The Compaq ProfileMe approach addresses the problem of accurately attributing events to instructions by sampling instructions rather than events [5,6]. An instruction is chosen to be profiled whenever the instruction counter overflows a specified random threshold.…”

Section: Accuracy Issuesmentioning

confidence: 99%

A Comparison of Counting and Sampling Modes of Using Performance Monitoring Hardware

Moore¹

2002

Lecture Notes in Computer Science

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Abstract. Performance monitoring hardware is available on most modern microprocessors in the form of hardware counters and other registers that record data about processor events. This hardware may be used in counting mode, in which aggregate events counts are accumulated, and/or in sampling mode, in which time-based or event-based sampling is used to collect profiling data. This paper discusses uses of these two modes and considers the issues of efficiency and accuracy raised by each. Implications for the PAPI cross-platform hardware counter interface are also discussed.

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ProfileMe: hardware support for instruction-level profiling on out-of-order processors

Cited by 145 publications

References 12 publications

Scalable Analysis Techniques for Microprocessor Performance Counter Metrics

Scalable Analysis Techniques for Microprocessor Performance Counter Metrics

Dissecting On-Node Memory Access Performance: A Semantic Approach

A Comparison of Counting and Sampling Modes of Using Performance Monitoring Hardware

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