Processor Microarchitecture: An Implementation Perspective

González, Antonio; Latorre, Fernando; Magklis, Grigorios

doi:10.2200/s00309ed1v01y201011cac012

Cited by 35 publications

(18 citation statements)

References 30 publications

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“…The CG-OoO processor introduces the Skipahead issue model. In OoO and CG-OoO, in-flight instructions are maintained in queues that are partly RAM and partly CAM tables (González et al 2010). For the InO model, instructions are held in a small FIFO buffer.…”

Section: Instruction Schedulingmentioning

confidence: 99%

CG-OoO

Mohammadi

Aamodt

Dally

2017

ACM Trans. Archit. Code Optim.

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We introduce the Coarse-Grain Out-of-Order (CG-OoO) general-purpose processor designed to achieve close to In-Order (InO) processor energy while maintaining Out-of-Order (OoO) performance. CG-OoO is an energy-performance-proportional architecture. Block-level code processing is at the heart of this architecture; CG-OoO speculates, fetches, schedules, and commits code at block-level granularity. It eliminates unnecessary accesses to energy-consuming tables and turns large tables into smaller, distributed tables that are cheaper to access. CG-OoO leverages compiler-level code optimizations to deliver efficient static code and exploits dynamic block-level and instruction-level parallelism. CG-OoO introduces Skipahead, a complexity effective, limited out-of-order instruction scheduling model. Through the energy efficiency techniques applied to the compiler and processor pipeline stages, CG-OoO closes 62% of the average energy gap between the InO and OoO baseline processors at the same area and nearly the same performance as the OoO. This makes CG-OoO 1.8× more efficient than the OoO on the energy-delay product inverse metric. CG-OoO meets the OoO nominal performance while trading off the peak scheduling performance for superior energy efficiency.

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Section: Instruction Schedulingmentioning

confidence: 99%

CG-OoO

Mohammadi

Aamodt

Dally

2017

ACM Trans. Archit. Code Optim.

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“…This choice of machines corresponds to configurations that are currently most often used by researchers for evolutionary experiments, either as standalone computers, or as end-nodes in a hybrid distributed evolutionary architecture. This also allows to study in detail the most interesting range, from 4-core to 16-core machines, with and without hyper-threading technology [8,29], and investigate relationships between the number of cores, threads, and the resulting performance.…”

Section: Multithreading Performancementioning

confidence: 99%

“…2: a linear slope for 1-4 threads and a nearly constant performance for 4+ threads. Configurations 4/8-W7, 4/8-W8, and 16/32-L feature hyper-threading technology (Intel's simultaneous multithreading implementation, SMT [8,29]) and can execute two simultaneous threads on each core, with slightly less performance compared to one thread per core, as additional threads share the same CPU hardware resources. This technology yields two nearly linear slopes: one for increasing the number of threads up to the number of physical cores, and another, less steep slope, up to twice the number of cores.…”

Section: Simulation and Evolutionmentioning

confidence: 99%

Multithreaded computing in evolutionary design and in artificial life simulations

Komosiński

Ulatowski

2016

J Supercomput

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This article investigates low-level and high-level multithreaded performance of evolutionary processes that are typically employed in evolutionary design and artificial life. Computations performed in these areas are specific because evaluation of each genotype usually involves time-consuming simulation of virtual environments and physics. Computational experiments have been conducted using the Framsticks simulator running a multithreaded version of a standard evolutionary experiment. Tests carried out on five diverse machines and two operating systems demonstrated how low-level performance depends on the number of physical and logical CPU cores and on the number of threads. Two string implementations have been compared, and their raw performance turned out to fundamentally differ in a multithreading setup. To improve high-level performance of parallel evolutionary algorithms, i.e. the quality of optimized solutions, a new distribution scheme that is especially useful and efficient for complex representations of solutions-the convection distribution-has been introduced. This new distribution scheme has been compared against a random distribution of genotypes among threads that carry out evolutionary processes.

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“…34 We denote the consumption per tag array access involved as L.r.tag and the consumption per data array reading as L.r.line. The sum of the two prior values is referred to L.r and the consumption involved in accessing the cache to perform a writing as L.w.…”

Section: Energy Modelmentioning

confidence: 99%

Reducing Cache Hierarchy Energy Consumption by Predicting Forwarding and Disabling Associative Sets

Carazo

Apolloni

Castro

et al. 2012

J CIRCUIT SYST COMP

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The first level data cache in modern processors has become a major consumer of energy due to its increasing size and high frequency access rate. In order to reduce this high energy consumption, we propose in this paper a straightforward filtering technique based on a highly accurate forwarding predictor. Specifically, a simple structure predicts whether a load instruction will obtain its corresponding data via forwarding from the load-store structure -thus avoiding the data cache access -or if it will be provided by the data cache. This mechanism manages to reduce the data cache energy consumption by an average of 21.5% with a negligible performance penalty of less than 0.1%. Furthermore, in this paper we focus on the cache static energy consumption too by disabling a portion of sets of the L2 associative cache. Overall, when merging both proposals, the combined LI and L2 total energy consumption is reduced by an average of 29.2% with a performance penalty of just 0.25%.

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Processor Microarchitecture: An Implementation Perspective

Cited by 35 publications

References 30 publications

CG-OoO

CG-OoO

Multithreaded computing in evolutionary design and in artificial life simulations

Reducing Cache Hierarchy Energy Consumption by Predicting Forwarding and Disabling Associative Sets

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