Processor-memory co-exploration driven by a Memory-Aware Architecture Description Language

Mishra, Prabhat; Grun, Peter; Dutt, Nikil; Nicolau, Alexandru

doi:10.1109/icvd.2001.902642

Cited by 19 publications

(12 citation statements)

References 17 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…very accurate low level models implemented by HDL 2 and ADL 3 [10]. Such models are mainly used by designers of processors, simulators and compilers but rarely by high level programmers because of their high complexity.…”

Section: Figure 2 Two Examples Of Architecture Graphmentioning

confidence: 99%

From algorithm and architecture specifications to automatic generation of distributed real-time executives: a seamless flow of graphs transformations

Grandpierre

Sorel

2003

First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings.

View full text Add to dashboard Cite

This paper presents a seamless flow of transformations which performs dedicated distributed executive generation from a high level specification of a pair: algorithm, architecture. This work is based upon graph models and graph transformations and is part of the AAA methodology. We present an original architecture model which allows to perform accurate sequencer modeling, memory allocation, and heterogeneous inter-processor communications for both modes shared memory and message passing. Then we present the flow of transformations that leads to the automatic generation of dedicated real-time distributed executives which are deadlock free. This transformation flow has been implemented in a system level CAD software tool called SynDEx.

show abstract

Section: Figure 2 Two Examples Of Architecture Graphmentioning

confidence: 99%

From algorithm and architecture specifications to automatic generation of distributed real-time executives: a seamless flow of graphs transformations

Grandpierre

Sorel

2003

First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings.

View full text Add to dashboard Cite

show abstract

“…In order to efficiently design customized processor cores, abstract Architecture Description Languages like EXPRESSION [10], ISDL [11], LISA [12], MIMOLA [13] and nML [14] have become popular. Basically, those environments which generate fast simulators with good system integration capabilities could have been used for this work.…”

Section: Related Workmentioning

confidence: 99%

Retargetable generation of TLM bus interfaces for MP-SoC platforms

Wieferink

Leupers

Ascheid

et al. 2005

Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

View full text Add to dashboard Cite

In order to meet flexibility, performance and energy efficiency constraints, future SoC (System-on-Chip) designs will contain an increasing number of heterogeneous processor cores combined with a complex communication architecture. Optimal platforms are obtained by customizing both computation and communication modules to the application's needs. In our design flow both kinds of SoC modules are automatically derived from abstract specifications. This work focuses on generating the communication adaptors, which are tailored to the processor as well as to the bus side. For early system simulation, the adaptors are capable of bridging an abstraction gap by implementing a bus interface state machine. The generated processor cores, adaptors and bus nodes are applied in the exemplary design of a JPEG decoding platform.

show abstract

“…First, fast analytical models have been proposed to prune very distinct design options using high level languages (e.g. C or C++) [17], [5]. Second, transaction-level modelling in SystemC, both at the academic [18], [21] and industrial level [16], [6], have enabled more accuracy in system-level simulation at the cost of sacrificing simulation speed (circa 100-200 Khz).…”

Section: Related Workmentioning

confidence: 99%

A Complete Multi-Processor System-on-Chip FPGA-Based Emulation Framework

Valle

Atienza

Magan

et al. 2006

2006 IFIP International Conference on Very Large Scale Integration

View full text Add to dashboard Cite

Abstract-With the growing complexity in consumer embedded products and the improvements in process technology, Multi-Processor System-On-Chip (MPSoC) architectures have become widespread. These new systems are very complex to design as they must execute multiple complex real-time applications (e.g. video processing, or videogames), while meeting several additional design constraints (e.g. energy consumption or time-to-market). Therefore, mechanisms to efficiently explore the different possible HW-SW design interactions in complete MPSoC systems are in great need. In this paper, we present a new FPGA-based emulation framework that allows designers to rapidly explore a large range of MPSoC design alternatives at the cycle-accurate level. Our results show that the proposed framework is able to extract a number of critical statistics from processing cores, memory and interconnection systems, with a speed-up of three orders of magnitude compared to cycleaccurate MPSoC simulators.

show abstract

Processor-memory co-exploration driven by a Memory-Aware Architecture Description Language

Cited by 19 publications

References 17 publications

From algorithm and architecture specifications to automatic generation of distributed real-time executives: a seamless flow of graphs transformations

From algorithm and architecture specifications to automatic generation of distributed real-time executives: a seamless flow of graphs transformations

Retargetable generation of TLM bus interfaces for MP-SoC platforms

A Complete Multi-Processor System-on-Chip FPGA-Based Emulation Framework

Contact Info

Product

Resources

About