Processor elements for the standard cell implementation of residue number systems

A high performance RNS multiply-accumulate unit

“…In our 18x18+36-bits precision MAC architecture, two 16-bit forward converters and one 32-bit reverse converter are required. It has been shown in [4] that a forward converter for the above moduli set has a latency of 4.5 ns when precision and process technology are scaled down to 18 bits and 0.35 micron respectively. A reverse converter for the same moduli set has a latency of 5.625 ns when precision and process technology are scaled down to 36 bits and 0.35 micron respectively [5].…”