Processing data where it makes sense: Enabling in-memory computation

Mutlu, Onur; Ghose, Saugata; Gómez-Luna, Juan; Ausavarungnirun, Rachata

doi:10.1016/j.micpro.2019.01.009

Cited by 169 publications

(95 citation statements)

References 20 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The latency and energy associated with accessing data from the memory units are key performance bottlenecks for a range of applications, in particular, for the increasingly prominent AI-related workloads. [11] The energy cost associated with moving data is a key challenge for both severely energy constrained mobile and edge computing as well as high-performance computing in a cloud environment due to cooling constraints. The current approaches, such as using hundreds of processors in parallel [12] or application-specific processors, [13] are not likely to fully overcome the challenge of data movement.…”

Section: In-memory Computingmentioning

confidence: 99%

Memristors—From In‐Memory Computing, Deep Learning Acceleration, and Spiking Neural Networks to the Future of Neuromorphic and Bio‐Inspired Computing

Mehonić¹,

Sebastian

Rajendran

et al. 2020

Advanced Intelligent Systems

161

109

View full text Add to dashboard Cite

Three factors are currently driving the main developments in artificial intelligence (AI): availability of vast amounts of data, continuous growth in computing power, and algorithmic innovations. Graphics processing units (GPUs) have been demonstrated as effective co-processors for the implementation of machine learning (ML) algorithms based on deep learning (DL). Solutions based on DL and GPU implementations have led to massive improvements in many AI tasks, but have also caused an exponential increase in demand for computing power. Recent analyses show that the demand for computing power has increased by a factor of 300 000 since 2012, and the estimate is that this demand will double every 3.4 months-at a much faster rate than improvements made historically through Moore's scaling (a sevenfold improvement over the same period of time). [1] At the same time, Moore's law has been slowing down significantly for the last few years, [2] as there are strong indications that we will not be able to continue scaling down complementary metal-oxide-semiconductor (CMOS) transistors. This calls for the exploration of alternative technology roadmaps for the development of scalable and efficient AI solutions. Transistor scaling is not the only way to improve computing performance. Architectural innovations, such as GPUs, field-programmable arrays (FPGAs), and application-specific integrated circuits (ASICs), have all significantly advanced the ML field. [3] A common aspect of modern computing architectures for ML is a move away from the classical von-Neumann architecture that physically separates memory and computing. This approach yields a performance bottleneck that is often the main reason for both energy and speed inefficiency of ML implementations on conventional hardware platforms due to

show abstract

Section: In-memory Computingmentioning

confidence: 99%

Memristors—From In‐Memory Computing, Deep Learning Acceleration, and Spiking Neural Networks to the Future of Neuromorphic and Bio‐Inspired Computing

Mehonić¹,

Sebastian

Rajendran

et al. 2020

Advanced Intelligent Systems

161

109

View full text Add to dashboard Cite

show abstract

“…Many studies have already pointed out the memory bottleneck problem and highlighted the need to shift the paradigm to data centric computing [14], [15]. They have shown that the consideration of PIM-specific constraints, a new architecture for the PIM, the set of memory intensive benchmarks to benefit from the PIM and the methods to accurately identify the PIM offloading candidates are necessary.…”

Section: Related Workmentioning

confidence: 99%

“…They have shown that the consideration of PIM-specific constraints, a new architecture for the PIM, the set of memory intensive benchmarks to benefit from the PIM and the methods to accurately identify the PIM offloading candidates are necessary. Also, the simulation infrastructure to measure the performance of the PIM should be established [14], [15].…”

Section: Related Workmentioning

confidence: 99%

Making Better Use of Processing-in-Memory Through Potential-Based Task Offloading

Kim

Rhee

2020

IEEE Access

View full text Add to dashboard Cite

There is an increasing demand for a novel computing structure for data-intensive applications such as artificial intelligence and virtual reality. The processing-in-memory (PIM) is a promising alternative to reduce the overhead caused by data movement. Many studies have been conducted on the utilization of the PIM taking advantage of the bandwidth increased by the through silicon via (TSV). One approach is to design an optimized PIM architecture for a specific application, the other is to find the tasks that will be more advantageous when offloading to PIM. The goal of this paper is to make the PIM, a newly introduced technology, be easily applied to various applications. The programmable GPU-based PIM is the target system. The essential but simple task offloading conditions are proposed to secure as many candidate tasks as possible when there is any potential benefit from the PIM. The PIM design options then are explored reflecting the characteristics of the candidate tasks actively. When determining offloading conditions, it is difficult to simultaneously consider three time-energy-power objectives. Thus, the problem is divided into two sub-problems. The first offloading condition is designed based on time-energy constraints, whereas the second offloading condition is modeled to satisfy time-power constraints. During the whole processes, the offloading conditions and the PIM design options are carefully configured in a complementary manner to reduce the tasks that are excluded from the offloading. In the simulation results, the suitability of the modeled two offloading conditions and the proposed PIM design are verified using various benchmarks and then, they are compared with previous works in terms of processing speed and energy. INDEX TERMS High bandwidth memory, near-data-processing, processing-in-memory, task offloading. I. INTRODUCTION Recently, more and more attention is paid to applications that require massive data processing, such as artificial intelligence and virtual reality. The parallelism of the graphic processing unit (GPU) has been used to increase the processing speed for such applications. However, improving efficiency in terms of data movement has not been a big concern [1]. Therefore, there is an increasing demand for a novel computing structure optimized to the execution of data-intensive applications. The near-data-processing (NDP), which puts the processing unit close to the data, is a promising alternative for reducing the overhead caused by data movement. When the processor is near memory, it is defined as a processing-in-memory (PIM). The associate editor coordinating the review of this manuscript and approving it for publication was Cihun-Siyong Gong. An example is the packaging of a processing unit within a memory module or inside a DRAM chip. Recently, the technology of the through silicon via (TSV) enables CPU, GPU or hardware accelerator to be mounted on logic die of 3-dimensional stacked memory. Thanks to this, PIM technology, which vertically stacks DRAM and a logic die with pr...

show abstract

“…Allowing PBF to modify these code pages enables dynamic code rewriting [62]. PBF can also be used for replicating data between hosts [82] or within a host [18], checkpointing [16], persistent memory logging [79], memory compression [63] and encryption [33], near-memory processing [55], offloading memory management tasks, etc. Table 2.…”

Section: Other Use Casesmentioning

confidence: 99%

Project PBerry

Calciu

Puddu

Kolli

et al. 2019

Proceedings of the Workshop on Hot Topics in Operating Systems

Self Cite

View full text Add to dashboard Cite

Recent research efforts propose remote memory systems that pool memory from multiple hosts. These systems rely on the virtual memory subsystem to track application memory accesses and transparently offer remote memory to applications. We outline several limitations of this approach, such as page fault overheads and dirty data amplification. Instead, we argue for a fundamentally different approach: leverage the local host's cache coherence traffic to track application memory accesses at cache line granularity. Our approach uses emerging cache-coherent FPGAs to expose cache coherence events to the operating system. This approach not only accelerates remote memory systems by reducing dirty data amplification and by eliminating page faults, but also enables other use cases, such as live virtual machine migration, unified virtual memory, security and code analysis. All of these use cases open up many promising research directions. CCS Concepts • Hardware → Hardware accelerators; • Software and its engineering → Distributed memory.

show abstract

Processing data where it makes sense: Enabling in-memory computation

Cited by 169 publications

References 20 publications

Memristors—From In‐Memory Computing, Deep Learning Acceleration, and Spiking Neural Networks to the Future of Neuromorphic and Bio‐Inspired Computing

Memristors—From In‐Memory Computing, Deep Learning Acceleration, and Spiking Neural Networks to the Future of Neuromorphic and Bio‐Inspired Computing

Making Better Use of Processing-in-Memory Through Potential-Based Task Offloading

Project PBerry

Contact Info

Product

Resources

About