Process windows for convenient in-process monitoring of oxide and polysilicon etches

Golshan, K.; Harward, Matt

doi:10.1109/icmts.1993.292914

ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures

DOI: 10.1109/icmts.1993.292914

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Process windows for convenient in-process monitoring of oxide and polysilicon etches

K. Golshan

Matt Harward

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Strategy to optimize the development, use, and dimension of test structures to control defect appearance in backend process steps

Hess¹

Proceedings of 1994 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (ASMC)

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To inspect and classify defects occurring during backend process steps, this paper describes a comprehensive methodology how to develop, use, and dimension test structures and how to optimize their organization inside given test chip boundaries. Starting point is the description of process steps and known types of defects. According to existing design rules different test structures will be designed and arranged as (in-line) process monitors inside a checkerboard framework using standard boundary pads.

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Strategy to optimize the development, use, and dimension of test structures to control defect appearance in backend process steps

Hess¹

Proceedings of 1994 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (ASMC)

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show abstract

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Process windows for convenient in-process monitoring of oxide and polysilicon etches

Cited by 1 publication

References 0 publications

Strategy to optimize the development, use, and dimension of test structures to control defect appearance in backend process steps

Strategy to optimize the development, use, and dimension of test structures to control defect appearance in backend process steps

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