Process variation-aware performance analysis of asynchronous circuits

Raji, Mohsen; Ghavami, Behnam; Pedram, Hossein; Zarandi, Hamid R.

doi:10.1016/j.mejo.2009.12.013

Cited by 5 publications

(6 citation statements)

References 16 publications

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“…However, adaptations of asynchronous timing models already started to deal with process variations, as proposed e.g. by Raji et al [53]. The basic idea of the cited work is to change the often used deterministic Timed Petri Nets (TPN) model to describe asynchronous concurrent behavior by probabilistic models such as the Variant-Timed Petri Net (VPTN) model [53].…”

Section: Robustness To Process and Temperaturementioning

confidence: 99%

Robust and Energy-Efficient Hardware: The Case for Asynchronous Design

Calazans

Rodolfo

Sartori

2021

JICS

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The current technologies behind the design of semiconductor integrated circuits allow embedding billions of components in a singe silicon die, enabling the construction of very complex circuits in a tiny space, dissipating little energy and producing huge amounts of useful computational work. However, the current levels of integration for electronic components in silicon and similar materials are not easily managed, as parameter variations grow steadily, making the design tasks increasingly challenging. Synchronous techniques have dominated the digital system design landscape for many decades, but their costs are increasingly hard to cope with. Asynchronous design and particularly quasi-delay insensitive design promises to deal with the same challenges more gracefully in current advanced nodes, and possibly irrevocably in future technology nodes. This article proposes a review of the state of the art in using asynchronous circuit design techniques to achieve energy-efficient and robust digital circuit and system design. In particular, the definition of a robust digital circuit comprises addressing several aspects to which a digital system design is expected to be robust to, including: (1) voltage variations; (2) process variations; (3) temperature variations; (4) circuit aging. Besides addressing energy-efficiency and all the mentioned robustness aspects, this work also approaches some of the state-of-the-art tools available to deal with asynchronous design, and points to desirable research development to be conducted in these subjects in the future.

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Section: Robustness To Process and Temperaturementioning

confidence: 99%

Robust and Energy-Efficient Hardware: The Case for Asynchronous Design

Calazans

Rodolfo

Sartori

2021

JICS

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“…In order to overcome issues such as channel crosstalk, clock feedthrough and power wasting, an asynchronous mode of digital low-pass ltering was chosen [14,15]. The last stage of the ROIC channel of Fig.…”

Section: Digital First-order Filteringmentioning

confidence: 99%

“…In the present case, the multi-channel system we deal with is an infrared (IR) gas analyzer. Its principle of operation is based on the spectroscopic gas Preprint submitted to Microprocessors and Microsystems: embedded hardware designDecember 15,2011 http://dx.doi.org/10.1016/j.micpro.2012.02.011 recognition [5], which is done by means of passing an IR light beam through a chamber with the gas under test. An array of IR sensors and optical lters on the chamber's output measures the light power on dierent infrared frequencies.…”

Section: Introductionmentioning

confidence: 99%

Design and modeling of a low-power multi-channel integrated circuit for infrared gas recognition

Sutula

Ferrer

Serra-Graells

2012

Microprocessors and Microsystems

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The design and high-level modeling of a multi-channel integrated circuit for infrared gas recognition suitable for low-power consumption are presented. The thermal compensation and independent programmability methods are used in all the main channel stages: sensor biasing, high-pass ltering and pre-amplication, blind cancellation, lock-in demodulation and A/D conversion. CMOS transistor subthreshold operation and circuit reuse techniques are widely applied in order to obtain a low-power and compact channel realization. Experimental results are presented for a 340µm×880µm channel integrated in 0.35µm CMOS technology reporting good agreement with electrical and higher level simulations.

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“…There are many techniques to design dual-V th synchronous circuits (Srivastava and Sylvester, 2004). However, these techniques cannot be applied directly to asynchronous logic in the same way that it can be done for synchronous circuits (Raji et al , 2010). It is due to because of the fact that it is difficult to define or to identify a critical path in asynchronous circuits, where it starts, where it stops, at least with a computer-aided design tool that has been designed for synchronous circuits.…”

Section: Introductionmentioning

confidence: 99%

“…However, the work does not consider the impacts of process variation. Earlier, we introduced a statistical leakage power reduction method for asynchronous circuits by using dual-V th technique (Raji et al , 2010). However, all the random variations are modeled as Gaussian processes without considering spatial correlation.…”

Section: Introductionmentioning

confidence: 99%

Spatial correlation-aware statistical dual-threshold voltage design of template-based asynchronous circuits

Ghavami

2018

COMPEL

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Purpose Power consumption is a top priority in high-performance asynchronous circuit design today. The purpose of this study is to provide a spatial correlation-aware statistical dual-threshold voltage design method for low-power design of template-based asynchronous circuits. Design/methodology/approach In this paper, the authors proposed a statistical dual-threshold voltage design of template-based asynchronous circuits considering process variations with spatial correlation. The utilized circuit model is an extended Timed Petri-Net which captures the dynamic behavior of the asynchronous circuit with statistical delay and power values. To have a more comprehensive framework, the authors model the spatial correlation information of the circuit. The authors applied a genetic optimization algorithm that uses a two-dimensional graph to calculate the power and performance of each threshold voltage assignment. Findings Experimental results show that using this statistically aware optimization, leakage power of asynchronous circuits can be reduced up to 3X. The authors also show that the spatial correlation may lead to large errors if not being considered in the design of dual-threshold-voltage asynchronous circuits. Originality/value The proposed framework is the scheme giving a low-power design of asynchronous circuits compared to other schemes. The comparison exhibits that the proposed method has better results in terms of performance and power. To consider the process variations with spatial correlation, the authors apply the principle component analysis method to transform the correlated variables into uncorrelated ones.

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Process variation-aware performance analysis of asynchronous circuits

Cited by 5 publications

References 16 publications

Robust and Energy-Efficient Hardware: The Case for Asynchronous Design

Robust and Energy-Efficient Hardware: The Case for Asynchronous Design

Design and modeling of a low-power multi-channel integrated circuit for infrared gas recognition

Spatial correlation-aware statistical dual-threshold voltage design of template-based asynchronous circuits

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