Process Technology Variation

Kuhn, Kelin J.; Giles, M.D.; Becher, D.; Kolar, Pramod; Kornfeld, A.; Kotlyar, R.; T., S.; Maheshwari, A.; Mudanai, S.

doi:10.1109/ted.2011.2121913

Cited by 329 publications

(128 citation statements)

References 26 publications

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“…As the transistor size shrinks into the submicron domain, it becomes more difficult and expensive to keep the uniformity of their electrical characteristics due to process variation -a challenge that is faced by every FPGAs user [9]. To guarantee the physical timing performance and reliability of FPGA products, either the physical yield of FPGAs chips would be compromised through a more vigorous manufacturing test, or a more conservative timing model has to be used to take variation into account [1]. Therefore, A method based on placement or routing to optimize the performance of FPGA without changing the fabrication process is preferred.…”

Section: Introductionmentioning

confidence: 99%

Mitigation of process variation effect in FPGAs with partial rerouting method

Guan

Wong

Chaudhuri

et al. 2014

IEICE Electron. Express

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Abstract:In this paper, the FPGA routing process is explored to mitigate and take advantage of the effect of delay variability due to process variation. A new method called partial rerouting is proposed in this paper to improve the timing performance based on process variation and reduce the execution time. By only rerouting a small number of critical and near-critical paths, about 6.3% timing improvement can be achieved by partial rerouting method. At the same time, partial rerouting can speed up the routing process by 9 times compared with full chipwise with 100 target FPGAs (variation maps). Moreover, the partial rerouting enables a trade-off between product yield and routing speed.

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Section: Introductionmentioning

confidence: 99%

Mitigation of process variation effect in FPGAs with partial rerouting method

Guan

Wong

Chaudhuri

et al. 2014

IEICE Electron. Express

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“…Variability sources are usually classified in two groups, systematic and random [2]. The first group cause deterministic shifts in device parameters, related to different manufacturing process conditions or critical process limitations [3]. For instance, one type of systematic variation is related to the difficulty of printing lines narrower than the wavelength of the light that it is used to print them [4].…”

Section: Introductionmentioning

confidence: 99%

“…Both effects may affect a design at any time in an unpredictable manner. Random Dopant Fluctuation (RDF) is usually assumed to be the main variability source [1,3,5]. Although systematic variations can be mitigated through the employment of process control or special design techniques, i.e.…”

Section: Introductionmentioning

confidence: 99%

Systematic and random variability analysis of two different 6T-SRAM layout topologies

Amat

Amatllé

Fernandez

et al. 2013

Microelectronics Journal

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a b s t r a c tThis paper studies the device variability influence on 6T-SRAM cells in a function of the regularity level of their layout. Systematic and random variations have been analyzed when these memory circuits are implemented on a 45 nm technology node. The NBTI aging relevance on these cells has been also studied for two layout topologies and SNM has been seen as the parameter that suffers the highest impact with respect to cell aging and variability.

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“…The impact of forming gas annealing on the electrical characteristics of sulfur passivated Al 2 This study reports the impact of forming gas annealing (FGA) on the electrical characteristics of sulfur passivated, atomic layer deposited Al 2 O 3 gate dielectrics deposited on (110) oriented n-and p-doped In 0.53 Ga 0.47 As layers metal-oxide-semiconductor capacitors (MOSCAPs). In combination, these approaches enable significant Fermi level movement through the bandgap of both n-and p-doped In 0.53 Ga 0.47 As (110) MOSCAPs.…”

mentioning

confidence: 99%

The impact of forming gas annealing on the electrical characteristics of sulfur passivated Al2O3/In0.53Ga0.47As (110) metal-oxide-semiconductor capacitors

Peralagu

Millar

et al. 2017

Applied Physics Letters

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This study reports the impact of forming gas annealing (FGA) on the electrical characteristics of sulfur passivated, atomic layer deposited Al2O3 gate dielectrics deposited on (110) oriented n- and p-doped In0.53Ga0.47 As layers metal-oxide-semiconductor capacitors (MOSCAPs). In combination, these approaches enable significant Fermi level movement through the bandgap of both n- and p-doped In0.53Ga0.47 As (110) MOSCAPs. A midgap interface trap density (Dit) value in the range 0.87−1.8×1012 cm−2eV−10.87−1.8×1012 cm−2eV−1 is observed from the samples studied. Close to the conduction band edge, a Dit value of 3.1×1011 cm−2eV−13.1×1011 cm−2eV−1 is obtained. These data indicate the combination of sulfur pre-treatment and FGA is advantageous in passivating trap states in the upper half of the bandgap of (110) oriented In0.53Ga0.47 As. This is further demonstrated by a reduction in border trap density in the n-type In0.53Ga0.47 As (110) MOSCAPs from 1.8×1012 cm−21.8×1012 cm−2 to 5.3×1011 cm−25.3×1011 cm−2 as a result of the FGA process. This is in contrast to the observed increase in border trap density after FGA from 7.3×1011 cm−27.3×1011 cm−2 to 1.4×1012 cm−21.4×1012 cm−2 in p-type In0.53Ga0.47 As (110) MOSCAPs, which suggest FGA is not as effective in passsivating states close to the valence band edge

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Process Technology Variation

Cited by 329 publications

References 26 publications

Mitigation of process variation effect in FPGAs with partial rerouting method

Mitigation of process variation effect in FPGAs with partial rerouting method

Systematic and random variability analysis of two different 6T-SRAM layout topologies

The impact of forming gas annealing on the electrical characteristics of sulfur passivated Al2O3/In0.53Ga0.47As (110) metal-oxide-semiconductor capacitors

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