Process Optimization and Device Characterization of Nonvolatile Charge Trap Memory Transistors Using In–Ga–ZnO Thin Films as Both Charge Trap and Active Channel Layers

Yun, Da-Jeong; Kang, Hyun Seo; Yoon, Sung‐Min

doi:10.1109/ted.2016.2580220

Cited by 31 publications

(36 citation statements)

References 26 publications

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“…Finally, 90nm-thick aluminum (Al) is deposited by thermal evaporation as a gate metal for both TFTs. It is patterned by a lift-off process [4][5][6]. An optical microscopy image of the fabricated multilevel memory is shown in Fig.…”

Section: Fabricationmentioning

confidence: 99%

P‐50: Development of Multilevel Memory Consisting of Oxide TFTs

Yun

Lee

et al. 2017

Symp Digest of Tech Papers

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This paper proposes a multilevel memory circuit with a simple structure composed of two oxide thin film transistors (Ox-TFTs) and one capacitor. The proposed memory circuit utilizes low leakage current characteristics of the Ox-TFT. Simulation and measurement results confirm that the proposed memory circuit can achieve multilevel memory feature. Author Keywordsmultilevel memory; oxide thin film transistor (Ox-TFT); low leakage current P-50 / S.-H. Yun SID 2017 DIGEST • 1427

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Section: Fabricationmentioning

confidence: 99%

P‐50: Development of Multilevel Memory Consisting of Oxide TFTs

Yun

Lee

et al. 2017

Symp Digest of Tech Papers

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“…The basic working mechanism of photonic memories is that the photo‐induced charge carriers are trapped into or detrapped from the charge trapping layer across the interface between the active layer and trapping layer during the programming/erasing process, resulting in a shift of threshold voltage during the reading process. Therefore, the performance of OPTM significantly depends upon the non‐volatile bistability of the charge‐trapping layer and the charge transfer process during the charge‐trapping and reading process . However, majority researches of light programming memory currently focused on the design of the charge‐trapping layer to increase number of discrete charge‐trapping sites such as metallic or semiconducting nanoparticles to improve the memory performance .…”

Section: Introductionmentioning

confidence: 99%

“…[1] However, organic phototransistor memory (OPTM) currently showed unsatisfying performance such as small memory window and short retention time compared with memories with electric programming and erasing. [14] However, majority researches of light programming memory currently focused on the design of the charge-trapping layer to increase number of discrete charge-trapping sites such as metallic or semiconducting nanoparticles to improve the memory performance. [1,12,13] The basic working mechanism of photonic memories is that the photo-induced charge carriers are trapped into or detrapped from the charge trapping layer across the interface between the active layer and trapping layer during the programming/erasing process, [9] resulting in a shift of threshold voltage during the reading process.…”

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confidence: 99%

High‐Performance All‐Inorganic Perovskite‐Quantum‐Dot‐Based Flexible Organic Phototransistor Memory with Architecture Design

Yang

Liu

et al. 2019

Adv Elect Materials

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floating gate organic field effect transistors (OFET)-based memory has been considered to have the most application prospects. [1][2][3][4][5][6] These memories based on the electric programming and erasing have been extensively studied while further development of their practical application is restricted by the high programming/ erasing voltages, which motivates the introduce of the light programming as an exactly novel independent programming method. [7][8][9][10][11] The light programming offers a noncontact programming method and is orthogonal to the electrical read-out process, which provides efficient way to achieve higher accuracy and capacity (multilevel storage) with the high discrepancies between different storage levels. [1] However, organic phototransistor memory (OPTM) currently showed unsatisfying performance such as small memory window and short retention time compared with memories with electric programming and erasing. Moreover, in order to generate sufficient photo-induced charge carriers and subsequent trapped minority charges for large memory window, sufficient photon energy, light intensity (3.5−188 mW cm −2 ), and illumination time (1 s to continuously) was required, which also seriously hindered further development and application of photonic memory. [1,12,13] The basic working mechanism of photonic memories is that the photo-induced charge carriers are trapped into or detrapped from the charge trapping layer across the interface between the active layer and trapping layer during the programming/erasing process, [9] resulting in a shift of threshold voltage during the reading process. Therefore, the performance of OPTM significantly depends upon the non-volatile bistability of the charge-trapping layer and the charge transfer process during the charge-trapping and reading process. [14] However, majority researches of light programming memory currently focused on the design of the charge-trapping layer to increase number of discrete charge-trapping sites such as metallic or semiconducting nanoparticles to improve the memory performance. [15][16][17][18] Little attention has been given to two key factors, "trapped carriers effect" and "interface effect" which were related to the charge transfer process and notably impacted the A novel organic phototransistor memory (OPTM) with architecture design is fabricated with all-inorganic perovskite quantum dots (QDs) as charge trapping layer. The novel architecture enables ultrashort channel length and vertical the charge transfer to effectively suppress both trapped carriers effect and interface effect, two key factors which impact photonic memory performance. Additionally, perovskite QDs are introduced to function as both the charge trapping layer and a UV-light-responsive material that emits visible light that can be subsequently absorbed by the active layer, leading to efficient utilization of UV light to generate trapped charges. OPTM exhibits excellent memory properties under significantly improved light conditions, which is superior to previou...

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“…As a typical architecture of nonvolatile memory devices, a floating-gated a-IGZO TFT memory has been intensively investigated in recent years. Up to now, various materials have been explored as a floating gate (i.e., charge storage medium), such as dielectrics [14, 15], metal nanocrystals [16, 17], and semiconducting materials [18–21]. Since a-IGZO is a natural n-type semiconductor, and hole inversion is hardly realized in an a-IGZO TFT under a negative gate bias, therefore, the a-IGZO TFT memories usually have a poor erasing efficiency.…”

Section: Introductionmentioning

confidence: 99%

“…Nevertheless, Zhang et al [21] fabricated a TFT memory using a-IGZO as both the charge trapping layer (CTL) and the channel layer, which exhibited electrically programmable and erasable characteristics, as well as good data retention. Meanwhile, Yun et al also investigated the characteristics of the a-IGZO TFT memories with different compositional IGZO CTL, revealing a decreasing memory window with increasing the O 2 partial pressure (P O2 ) during sputtering deposition of the CTL [18]. In addition, Bak et al reported the performance of the a-IGZO TFT memories with various conductivity ZnO CTLs and inferred that the optimized electronic nature of bandgap structure for the ZnO CTL could be one of the most important factors to realize highly functional oxide TFT memories [20].…”

Section: Introductionmentioning

confidence: 99%

Voltage-Polarity Dependent Programming Behaviors of Amorphous In–Ga–Zn–O Thin-Film Transistor Memory with an Atomic-Layer-Deposited ZnO Charge Trapping Layer

Liu

Pei

et al. 2019

Nanoscale Res Lett

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Amorphous In–Ga–Zn-O (a-IGZO) thin-film transistor (TFT) memories are attracting many interests for future system-on-panel applications; however, they usually exhibit a poor erasing efficiency. In this article, we investigate voltage-polarity-dependent programming behaviors of an a-IGZO TFT memory with an atomic-layer-deposited ZnO charge trapping layer (CTL). The pristine devices demonstrate electrically programmable characteristics not only under positive gate biases but also under negative gate biases. In particular, the latter can generate a much higher programming efficiency than the former. Upon applying a gate bias pulse of +13 V/1 μs, the device shows a threshold voltage shift (ΔVth) of 2 V; and the ΔVth is as large as −6.5 V for a gate bias pulse of −13 V/1 μs. In the case of 12 V/1 ms programming (P) and −12 V/10 μs erasing (E), a memory window as large as 7.2 V can be achieved at 103 of P/E cycles. By comparing the ZnO CTLs annealed in O2 or N2 with the as-deposited one, it is concluded that the oxygen vacancy (VO)-related defects dominate the bipolar programming characteristics of the TFT memory devices. For programming at positive gate voltage, electrons are injected from the IGZO channel into the ZnO layer and preferentially trapped at deep levels of singly ionized oxygen vacancy (VO +) and doubly ionized oxygen vacancy (VO 2+). Regarding programming at negative gate voltage, electrons are de-trapped easily from neutral oxygen vacancies because of shallow donors and tunnel back to the channel. This thus leads to highly efficient erasing by the formation of additional ionized oxygen vacancies with positive charges.

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Process Optimization and Device Characterization of Nonvolatile Charge Trap Memory Transistors Using In–Ga–ZnO Thin Films as Both Charge Trap and Active Channel Layers

Cited by 31 publications

References 26 publications

P‐50: Development of Multilevel Memory Consisting of Oxide TFTs

P‐50: Development of Multilevel Memory Consisting of Oxide TFTs

High‐Performance All‐Inorganic Perovskite‐Quantum‐Dot‐Based Flexible Organic Phototransistor Memory with Architecture Design

Voltage-Polarity Dependent Programming Behaviors of Amorphous In–Ga–Zn–O Thin-Film Transistor Memory with an Atomic-Layer-Deposited ZnO Charge Trapping Layer

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