Process-Dependence Analysis for Characteristic Improvement of Ring Oscillator Using 16-nm Bulk FinFET Devices

Su, Ping-Hsun; Li, Yiming

doi:10.1109/ted.2016.2582224

Cited by 4 publications

(1 citation statement)

References 16 publications

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“…16 thus suggests that even if becomes longer as a result of PIPB, it does not exceed 100 ∕3, in general. The chain for measurement typically consists of 10-100 inverters, which is equal to or larger than the typical [193], [195]- [199], Bulk-Fin [200]- [202], SOI-Planar [196], and SOI-Fin [203] devices. To increase the amount of data for the Fin case, the figure also shows a similar delay, but measured for inverters with Fan-Out of 1 (FO1).…”

Section: Invertermentioning

confidence: 99%

Scaling Trends of Digital Single-Event Effects: A Survey of SEU and SET Parameters and Comparison With Transistor Performance

Kobayashi

2021

IEEE Trans. Nucl. Sci.

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Section: Invertermentioning

confidence: 99%

Scaling Trends of Digital Single-Event Effects: A Survey of SEU and SET Parameters and Comparison With Transistor Performance

Kobayashi

2021

IEEE Trans. Nucl. Sci.

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Comprehensive Analysis of Source and Drain Recess Depth Variations on Silicon Nanosheet FETs for Sub 5-nm Node SoC Application

et al. 2020

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Excess source and drain (S/D) recess depth (T SD) variations were analyzed comprehensively as one of the most critical factors to DC/AC performances of sub 5-nm node Si-Nanosheet (NS) FETs for system-on-chip (SoC) applications. Variations of off-, on-state currents (I off , I on) in three-stacked NS channels and parasitic bottom transistor (tr pbt), gate capacitance (C gg), intrinsic switching delay time (τ d), and static power dissipation (P static) are investigated quantitatively according to the T SD variations. More S/D dopants diffuse into the tr pbt with the deeper T SD , so the I off and I on increase due to raised current flowing through the tr pbt. Especially, the I off of PFETs remarkably increases above the certain T SD (T SD,critical) compared to NFETs. Furthermore, the I on contribution of each channels having the T SD,critical is the largest at the top NS channel and the tr pbt has the ignorable I on contribution. Among the NS channels, the top (bottom) NS channel has the largest (smallest) I on contribution due to its larger (smaller) carrier density and velocity for both P-/NFETs. The C gg also increases with the deeper T SD by increasing parasitic capacitance, but fortunately, the τ d decreases simultaneously due to the larger increasing rate of the I on than that of the C gg for all SoC applications. However, the P static enormously increases with the deeper T SD , and low power application is the most sensitive to the T SD variations among the SoC applications. Comprehensive analysis of the inevitable tr pbt effects on DC/AC performances is one of the most critical indicators whether Si-NSFETs could be adopted to the sub 5-nm node CMOS technology.

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Analysis of In-Line Process Parameters of the Unity Gain Frequency of HKMG Bulk FinFET Devices

2018

IEEE Electron Device Lett.

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Process-Dependence Analysis for Characteristic Improvement of Ring Oscillator Using 16-nm Bulk FinFET Devices

Cited by 4 publications

References 16 publications

Scaling Trends of Digital Single-Event Effects: A Survey of SEU and SET Parameters and Comparison With Transistor Performance

Scaling Trends of Digital Single-Event Effects: A Survey of SEU and SET Parameters and Comparison With Transistor Performance

Comprehensive Analysis of Source and Drain Recess Depth Variations on Silicon Nanosheet FETs for Sub 5-nm Node SoC Application

Analysis of In-Line Process Parameters of the Unity Gain Frequency of HKMG Bulk FinFET Devices

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