Probabilistically bounded soft sphere detection for MIMO-OFDM receivers: algorithm and system architecture

Abstract

Abstract-Iterative soft detection and channel decoding for MIMO OFDM downlink receivers is studied in this work. Proposed inner soft sphere detection employs a variable upper bound for number of candidates per transmit antenna and utilizes the breath-first candidate-search algorithm. Upper bounds are based on probability distribution of the number of candidates found inside the spherical region formed around the received symbolvector. Detection accuracy of unbounded breadth-first candidatesearch is preserved while significant reduction of the search latency and area cost is achieved. This probabilistically bounded candidate-search algorithm improves error-rate performance of non-probabilistically bounded soft sphere detection algorithms, while providing smaller detection latency with same hardware resources. Prototype architecture of soft sphere detector is synthesized on Xilinx FPGA and for an ASIC design. Using area-cost of a single soft sphere detector, a level of processing parallelism required to achieve targeted high data rates for future wireless systems (for example, 1 Gbps data rate) is determined.

A Dominance-Based Soft-Input Soft-Output MIMO Detector With Near-Optimal Performance

“…, K, we need to compute the l.h.s. of a dominance condition for each survived node 9 of the level i − 1, namely compute (33), and subtract it from the remainder of the l.h.s., already computed in the pre-processing step. Also, (33) can be rewritten aš…”

“…In [32] the authors propose an exact Max-Log detector based on multiple hard SD steps (the number of needed steps is equal to the number of transmit antennas plus one) and a suboptimal solution, which needs only one hard SD step, leading to a remarkable complexity saving. Hardware implementations of SISO detectors based on SD have been proposed, such as the field-programmable gate array (FPGA) prototype and the ASIC synthesis in [33]. Furthermore, in [34] the authors extend the FSD [28] to the SISO case and propose a VLSI implementation.…”