Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches

Bi, Xiuyuan; Sun, Zhenyu; Li, Hai; Wu, Weiwei

doi:10.1145/2429384.2429401

Cited by 60 publications

(32 citation statements)

References 10 publications

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“…In all cases and across this entire error probability range, VEWs dramatically improve write energy compare with both the conventional baseline and a VOW with 64-bit subblock(same as [5]). We assume 50% bits within one sub-block will change in each write in VOW.…”

Section: B Resultsmentioning

confidence: 93%

“…Note that the proposed write completion circuit controls each bit independently which maximizes write efficiency. This is in contrast to the VOW architecture of Bi et al [5], which terminates writes at the granularity of an entire word (Fig. 5).…”

Section: A Implementation Detailsmentioning

confidence: 82%

“…A related mechanism for exploiting STT-RAM write stochasticity, verifyon-write (VOW), was recently proposed by Bi et al [5]. VOW is based on a similar insight to ours but has two important limitations that our work overcomes.…”

Section: Introductionmentioning

confidence: 87%

“…We also compare VEWs with the related verify-onwrite (VOW) [5] technique and with early-write termination (EWT) [4]. To directly compare all three techniques within the same context, we use the same MTJ parameters as in Tab.…”

Section: P -> a P W R I T E P -> P W R I T E C O N V E N T I O N A L mentioning

confidence: 99%

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Variable-energy write STT-RAM architecture with bit-wise write-completion monitoring

Zheng

Park

Orshansky

et al. 2013

International Symposium on Low Power Electronics and Design (ISLPED)

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Abstract-In this paper we demonstrate an energy-reduction strategy that relies on the stochastic long-tail nature of the STT-RAM write operation. To move away from the traditional worst-case approach, the per-cell write process is continuously monitored and is terminated as soon as each cell's state matches the written state. Since the average write duration is far shorter than the worstcase duration, the average write energy is significantly reduced by the proposed architecture. We developed a light-weight circuit for fast state change detection and bit-line shutdown and evaluated it using a compact STT-RAM model targeting an implementation in a 16nm technology node. Our analysis indicates that at the required write-error rate the proposed architecture reduces write energy by 87.3% − 99.5% depending on the write direction, and on average achieves 96.5% write energy saving in 16 SPEC CPU 2006 applications compared to conventional design. Compared to the best previously known architecture that exploits stochasticity (verify-on-write), we reduce write energy by approximately 6.5×.

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Section: B Resultsmentioning

confidence: 93%

Section: A Implementation Detailsmentioning

confidence: 82%

Section: Introductionmentioning

confidence: 87%

Section: P -> a P W R I T E P -> P W R I T E C O N V E N T I O N A L mentioning

confidence: 99%

See 2 more Smart Citations

Variable-energy write STT-RAM architecture with bit-wise write-completion monitoring

Zheng

Park

Orshansky

et al. 2013

International Symposium on Low Power Electronics and Design (ISLPED)

View full text Add to dashboard Cite

show abstract

“…Nevertheless, these techniques may degrade the STT-MRAM performance and thus limit its usages in high-speed and low-power working memory applications. In addition, the data write operation of STT-MRAM is highly asymmetric, that is, the cost for writing data bits 0 and 1 is different, owing to the intrinsic asymmetry of the STT effect [13,14,15]. From circuit design perspective, current NVMs generally employ the typical 1T1R (one access transistor connected in series with a storage element) cell structure, which results in source degeneration problem of the access transistor for writing different data bits into the memory cell due to the various bias conditions of the access transistor, again leading to asymmetric failure characteristics [16,17].…”

Section: Introductionmentioning

confidence: 99%

Extended coset decoding scheme for multi-bit asymmetric errors in non-volatile memories

Liu

Zhang

et al. 2017

IEICE Electron. Express

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Non-volatile memories (NVMs), such as Magnetic RAM and Resistive RAM, have been considered as the potential working or storage memories in the next generation computer architectures, thanks to the various merits, such as non-volatility, low power and high speed etc. However, new technology brings simultaneously new challenges, e.g. reliability issue, before practical applications. Compared with conventional memories, the errors in NVMs are generally asymmetric, resulting in different failure rates for 0-1 and 1-0 bit flipping. Error correcting codes (ECCs) are common solutions for protecting memories from errors. The most widely used ECCs are the single error correction and double error detection (SEC-DED) codes. Unfortunately, they are primarily designed for correcting symmetric errors and their error correction capabilities are limited to only one bit. Regarding the failure characteristics (e.g., multi-bit and asymmetric) of NVMs, conventional SEC-DED codes are not efficiently applicable. This paper proposes an extended coset decoding scheme for NVMs. Our simulation results with a Hamming code (with Hamming distance of only three) as an example show the effectiveness of the proposed decoding scheme. The proposed decoding scheme can also be extended to other linear block codes and is rather suitable for scenarios with multi-bit asymmetric error features.

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Circuit Design for Non-volatile Magnetic Memory

Kim

2021

Emerging Non-Volatile Memory Technologies

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Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches

Cited by 60 publications

References 10 publications

Variable-energy write STT-RAM architecture with bit-wise write-completion monitoring

Variable-energy write STT-RAM architecture with bit-wise write-completion monitoring

Extended coset decoding scheme for multi-bit asymmetric errors in non-volatile memories

Circuit Design for Non-volatile Magnetic Memory

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