Probabilistic Analysis of Power-Gating in Network-on-Chip Routers

Nasirian, Nasim; Soosahabi, Reza; Bayoumi, Magdy

doi:10.1109/tcsii.2018.2863268

Cited by 4 publications

(2 citation statements)

References 8 publications

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“…Fanni et al [11,29] studied an estimation model of power consumption to identify the regions of the design that can benefit from the application of power saving techniques. Nasirian et al [25] modeled the behaviour of router buffers using queuing theory to evaluate the effect of power gating on the overall power saving and power penalty on network-on-chip. To evaluate the proposed algorithm, they adopted a cycle accurate simulator.…”

Section: Related Workmentioning

confidence: 99%

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NeuPow

Nasser

Prévotet

et al. 2020

ACM Trans. Des. Autom. Electron. Syst.

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In this paper, we present a new, simple, accurate and fast power estimation technique that can be used to explore the power consumption of digital system designs at an early design stage. We exploit the machine learning techniques to aid the designers in exploring the design space of possible architectural solutions, and more specifically, their dynamic power consumption, which is application, technology, frequency and data stimuli dependent. To model the power and the behavior of digital components, we adopt the Artificial Neural Networks (ANNs), while the final target technology is Application Specific Integrated Circuit (ASIC). The main characteristic of the proposed method, called NeuPow, is that it relies on propagating the signals throughout connected ANN models to predict the power consumption of a composite system. Besides a baseline version of the NeuPow methodology that works for a given predefined operating frequency, we also derive an upgraded version that is frequency aware, where the same operating frequency is taken as additional input by the ANN models. To prove the effectiveness of the proposed methodology, we perform different assessments at different levels. Moreover, technology and scalability studies have been conducted, proving the NeuPow robustness in terms of these design parameters. Results show a very good estimation accuracy with less than 9% of relative error independently from the technology and the size/layers of the design. NeuPow is also delivering a speed-up factor of about 84× with respect to the classical power estimation flow.

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Section: Related Workmentioning

confidence: 99%

“…More flexible solutions focus on modeling, with the advantage of enabling power saving techniques. For instance, Nasirian et al [25] presented an approach for power gating management in network-on-chip designs, adopting a cycle accurate simulator. In general, trade-off among complexity of the models and accuracy should be pursued.…”

Section: Introductionmentioning

confidence: 99%

NeuPow

Nasser

Prévotet

et al. 2020

ACM Trans. Des. Autom. Electron. Syst.

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Dynamic idle core management and leakage current reuse in MPSoC platforms

Hossain

Savidis

2020

Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design

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Design and Implementation of a Efficient Router using X Y Algorithm

Geethanjali¹,

Rekha²

2021

IJDCN

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The engineering for on chip network configuration utilizing dynamic reconfiguration is an answer for Communication Interfaces, Chip cost ,Quality of Service, ensure adaptability of the organization. The proposed engineering powerfully arrange itself concerning Hardware Modules like switches, Switch based packet , information to a packet size with changing the correspondence situation and its prerequisites on run time. The NOC Architecture assumes urgent part while planning correspondence frameworks intended for SOC. The NOC engineering be better over traditional transport, mutual transport plan , cross bar interconnection design intended for on chip organizations. In a greater part of the NO C engineering contains lattice, torus or different geographies to plan solid switch. In any case, the greater part of the plans are neglects to advance a Quality of Service, blocking issues, cost, Chip as well as mostly plan throughput, region transparency with inactivity. Proposed plan we are planning a reconfigurable switch for network on chip plan that improve the correspondence performance. The proposed configuration dodges the restrictions of transport based interconnection plans which are frequently applied in part progressively reconfigurable FPGA plans. . With the assistance of this switch plan we can accomplish low inactivity and high information throughput.

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Probabilistic Analysis of Power-Gating in Network-on-Chip Routers

Cited by 4 publications

References 8 publications

NeuPow

NeuPow

Dynamic idle core management and leakage current reuse in MPSoC platforms

Design and Implementation of a Efficient Router using X Y Algorithm

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