Probabilistic analysis of cache memories and cache memories impacts on multi-core embedded systems

Guet, Fabrice; Santinelli, Luca; Mitard, J.

doi:10.1109/sies.2016.7509420

Cited by 6 publications

(7 citation statements)

References 14 publications

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“…Several works build on HEMs for multicore timing analysis, for bound estimation and online monitoring [23], [34], [35], [36]. On the industrial side, HEMs have also been exploited to produce timing evidence needed for certification on multicores [27], [37].…”

Section: Related Workmentioning

confidence: 99%

Much

Vilardell

Serra

Mezzetti

et al. 2021

Proceedings of the 36th Annual ACM Symposium on Applied Computing

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Section: Related Workmentioning

confidence: 99%

Much

Vilardell

Serra

Mezzetti

et al. 2021

Proceedings of the 36th Annual ACM Symposium on Applied Computing

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“…In the same vein, Diaz et al [38] build on HEM to produce an ILP-based contention model for an AURIX automotive microcontroller. Likewise, Santinelli et al [39], build on the HEM of a multicore system to derive probabilistic WCET estimates. Griffin et al [40] derive a method to select the HEM with highest contribution to software timing and predict execution time under unseen configurations.…”

Section: Related Workmentioning

confidence: 99%

HRM: Merging Hardware Event Monitors for Improved Timing Analysis of Complex MPSoCs

Vilardell

Serra

Santalla

et al. 2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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The Performance Monitoring Unit (PMU) in MP-SoCs is at the heart of the latest measurement-based timing analysis techniques in Critical Embedded Systems. In particular, hardware event monitors (HEMs) in the PMU are used as building blocks in the process of budgeting and verifying software timing by tracking and controlling access counts to shared resources. While the number of HEMs in current MPSoCs reaches hundreds, they are read via Performance Monitoring Counters whose number is usually limited to 4-8, thus requiring multiple runs of each experiment in order to collect all desired HEMs. Despite the effort of engineers in controlling the execution conditions of each experiment, the complexity of current MPSoCs makes it arguably impossible to completely remove the noise affecting each run. As a result, HEMs read in different runs are subject to different variability, and hence, those HEMs captured in different runs cannot be 'blindly' merged. In this work, we focus on the NXP T2080 platform where we observed up to 59% variability across different runs of the same experiment for some relevant HEMs (e.g. processor cycles). We develop a HEM reading and merging (HRM) approach to join reliably HEMs across different runs as a fundamental element of any measurement-based timing budgeting and verification technique. Our method builds on order statistics and the selection of an anchor HEM read in all runs to derive the most plausible combination of HEM readings that keep the distribution of each HEM and their relationship with the anchor HEM intact.

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“…We have suggested the use of interference generators in the past [5], as have others. Guet suggested generating parametric interference to the data cache [6], and Hwang notes the use of a virtual machine as an interference generator [7]. Iorga refers to their interference generators as "enemy programs" [8].…”

Section: ) Interference Generator Approach To Measuring Wcetmentioning

confidence: 99%

Measuring the Impact of Interference Channels on Multicore Avionics

VanderLeest

Thompson

2020

2020 AIAA/IEEE 39th Digital Avionics Systems Conference (DASC)

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Measurement-based analysis of software timing behavior provides important insight and evidence for flight certification of modern avionics systems. For multicore systems, however, this analysis is challenging due to interference effects from shared hardware resource usage. We present an approach to multicore timing analysis that uses interference generators to stress interference channels in multicore systems. The test methodology comprises two steps. First, platform characterization measures the sensitivity of the hardware and RTOS to targeted interference channels using a combination of interference generators. Second, software characterization measures the timing behavior of instrumented applications while interference is generated on shared resources.

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Probabilistic analysis of cache memories and cache memories impacts on multi-core embedded systems

Cited by 6 publications

References 14 publications

Much

Much

HRM: Merging Hardware Event Monitors for Improved Timing Analysis of Complex MPSoCs

Measuring the Impact of Interference Channels on Multicore Avionics

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