PRISM-II compiler and architecture

Wazlowski, M.; Agarwal, L.; Lee, T.; Smith, A.; Lam, E.Y.; Athanas, Peter; Silverman, H.F.; Ghosh, Sumit

doi:10.1109/fpga.1993.279484

Cited by 87 publications

(22 citation statements)

References 4 publications

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“…Major FCCM projects and systems will be briefly mentioned in this section. Those which were cited frequently are PRISM II [9] , MorphoSys [10] , PipeRench [11] , DISC [12] , OneChip [13] , GARP [14] , Chimera [15] , NAPA [16] , REMARC [17] and OneChip98 [18] . Their key-features are summarized in Tab.1.…”

Section: Previous Work On Reconfigurable Architecturementioning

confidence: 97%

The research and design of reconfigurable computing for Block cipher

Yang

Dai

Zhang

et al. 2008

J. Electron.(China)

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This paper describes a new specialized Reconfigurable Cryptographic for Block ciphers Architecture (RCBA). Application-specific computation pipelines can be configured according to the characteristics of the block cipher processing in RCBA, which delivers high performance for cryptographic applications. RCBA adopts a coarse-grained reconfigurable architecture that mixes the appropriate amount of static configurations with dynamic configurations. RCBA has been implemented based on Altera's FPGA, and representative algorithms of block cipher such as DES, Rijndael and RC6 have been mapped on RCBA architecture successfully. System performance has been analyzed, and from the analysis it is demonstrated that the RCBA architecture can achieve more flexibility and efficiency when compared with other implementations.

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Section: Previous Work On Reconfigurable Architecturementioning

confidence: 97%

The research and design of reconfigurable computing for Block cipher

Yang

Dai

Zhang

et al. 2008

J. Electron.(China)

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“…The FPGAs perform most of the computationally intensive portions of the code (10 percent of the program 90 percent of runtime in microprocessors) with high parallelism and the processor takes care of all other operations (90 percent of the code, 10 percent of runtime in microprocessors). This approach benefits from FPGA parallelism and specialization as well as the flexibility of the microprocessors to provide the best environment for implementing complicated DSP applications [23][24][25][26][27].…”

Section: Introductionmentioning

confidence: 99%

Run-Time Reconfigurable Systems for Digital Signal Processing Applications: A Survey

Shoa

Shirani

2005

J VLSI Sign Process Syst Sign Image Video Technol

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Today's digital signal processing (DSP) applications use computationally complex and/or adaptive algorithms and have stringent requirements in terms of speed, size, cost, power consumption, and throughput. Efficient hardware implementation techniques should be employed to meet the requirements of these applications. Run-Time Reconfiguration (RTR) is a promising technique for reducing the hardware required for implementing DSP systems as well as improving the performance, speed and power consumption of these systems. In this survey, we explain different issues in run-time reconfigurable systems and list the implemented systems which support run-time reconfiguration. We also describe different applications of run-time reconfiguration and discuss the improvements achieved by applying run-time reconfiguration.

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“…One of the first efforts to automatically map applications onto an FPGA was Splash [7], subsequently productized as the NAPA system [8]. Other automatic compiler systems for FPGA-based platforms include GARP [2], PRISM [24], and DEFACTO [1]. Modulo scheduling has been used [19,12] to map critical loops onto reconfigurable coprocessors.…”

Section: Related Workmentioning

confidence: 99%

Increasing hardware efficiency with multifunction loop accelerators

Fan

Kudlur

Park

et al. 2006

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis

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To meet the conflicting goals of high-performance low-cost embedded systems, critical application loop nests are commonly executed on specialized hardware accelerators. These loop accelerators are traditionally designed in a single-function manner, wherein each loop nest is implemented as a dedicated hardware block. This paper focuses on hardware sharing across loop nests by creating multifunction loop accelerators, or accelerators capable of executing multiple algorithms. A compiler-based system for automatically synthesizing multifunction loop accelerator architectures from C code is presented. We compare the effectiveness of three architecture synthesis approaches with varying levels of complexity: sum of individual accelerators, union of individual accelerators, and joint accelerator synthesis. Experiments show that multifunction accelerators achieve substantial hardware savings over combinations of singlefunction designs. In addition, the union approach to multifunction synthesis is shown to be effective at creating low-cost hardware by exploiting hardware sharing, while remaining computationally tractable.

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PRISM-II compiler and architecture

Cited by 87 publications

References 4 publications

The research and design of reconfigurable computing for Block cipher

The research and design of reconfigurable computing for Block cipher

Run-Time Reconfigurable Systems for Digital Signal Processing Applications: A Survey

Increasing hardware efficiency with multifunction loop accelerators

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