Prioritized Traversal: Efficient Reachability Analysis for Verification and Falsification

Abstract

Our experience with semi-exhaustive verification shows a severe degradation in usability for the corner-case bugs, where the tuning effort becomes much higher and recovery from dead-ends is more and more difficult. Moreover, when there are no bugs at all, shifting semi-exhaustive traversal to exhaustive traversal is very expensive, if not impossible. This makes the output of semi-exhaustive verification on non-buggy designs very ambiguous. Furthermore, since after the design fixes each falsification task needs to converge to full verification, there is a strong need for an algorithm that can handle efficiently both verification and falsification. We address these shortcomings with an enhanced reachability algorithm that is more robust in detecting corner-case bugs and that can potentially converge to exhaustive reachability. Our approach is similar to that of Cabodi et al. in partitioning the frontiers during the traversal, but differs in two respects. First, our partitioning algorithm trades quality for time resulting in a significantly faster traversal. Second, the subfrontiers are processed according to some priority function resulting in a mixed BFS/DFS traversal. It is this last feature that makes our algorithm suitable for both falsification and verification.

Achieving Speedups in Distributed Symbolic Reachability Analysis Through Asynchronous Computation

“…We used FORECAST [13] for this purpose. FORECAST is an industrial strength highperformance implementation of a BDD-based model checker developed at Intel, Haifa.…”

“…Other papers suggest reducing the space requirements for sequential symbolic reachability analysis by partitioning the work into several tasks [25,7,13]. However, these schemes use a single machine to sequentially handle one task at a time, while the other tasks are kept in external memory.…”

Reference model based RTL verification: an integrated approach

“…The first step is to verify that the reference model satisfies a higher-level specification. This problem is addressed by mainstream FV and is documented in a rich collection of papers both from academia and industry [1,2,7,8,12,13,15,16]. The second step is to verify that the reference model, in the presence of environmental constraints, does imply the RTL design implementation.…”

Verifying Very Large Industrial Circuits Using 100 Processes and Beyond

“…If no adequate slicer is found, it gradually applies more precise computations. We compare our hybrid algorithm with the fast estimating algorithm Est [5]. We show that our algorithm produces far fewer duplications.…”

“…In the first phase the algorithm employs the method Est [5] to search for an effective slicer. This method initially computes an estimate of the size of f ∧v and f ∧v, for each variable v in the support of f .…”