Principle of Nand Flash Memory

Aritome, S.

doi:10.1002/9781119132639.ch2

Cited by 3 publications

(2 citation statements)

References 12 publications

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“…9) As mentioned before, such HV devices require a significant area consumption, due to their enlarged Gate to Drain distance. It is expected that such area consumption will become one of the limiting factors to the overall area consumption in 3D NAND memory chips of the future, 10) even if all the periphery devices are fabricated at the bottom of the memory array (which is commonly used in nowadays state of the art solutions). 3,4,15,16) We propose to leverage the 3D structure of the FF [Fig.…”

Section: General Device For 3d Nand Peripheralsmentioning

confidence: 99%

“…It is expected that such HV devices require significant area consumption already today. 10) Additionally, the total number of memory layers in current 3D NAND is already >200, and expected to increase further, 11) requiring a corresponding increase of the HV peri devices. This poses significant challenges to the area consumption due to HV devices, and even the expected introduction of the wafer to wafer bonding approach 11,12) will not solve it.…”

Section: Introductionmentioning

confidence: 99%

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Compact thermally stable high voltage FinFET with 40 nm tox and lateral break-down >35 V for 3D NAND flash periphery application

Spessot,

Matagne,

Arimura

et al. 2024

Jpn. J. Appl. Phys.

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We propose for the first time a dedicated FinFET (FF) technology with specific optimization for tox>40nm and lateral break-down (LBD)>35V to replace the conventional planar high voltage (HV) transistors in the 3D NAND Flash periphery. We show significant current increase (>x2) and area saving per footprint, solving one of the key bottlenecks of future 3D NAND nodes. Fabrication of thermally stable prototypes is shown, with no significant impact on the overall fabrication complexity

show abstract

Section: General Device For 3d Nand Peripheralsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Compact thermally stable high voltage FinFET with 40 nm tox and lateral break-down >35 V for 3D NAND flash periphery application

Spessot,

Matagne,

Arimura

et al. 2024

Jpn. J. Appl. Phys.

View full text Add to dashboard Cite

show abstract

BOOSTER: Rethinking the erase operation of low-latency SSDs to achieve high throughput and less long latency

Fujimori¹,

Nomura²

2023

Proceedings of the 16th ACM International Conference on Systems and Storage

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IoT Device Identification Protocol based on Degraded Flash Memory

Vladimirov¹,

Berestovoy²

2020

Telecom IT

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Research subject. The article presents a protocol for identifying IoT devices developed by the authors and the results of its testing. Method. Simulation was performed to determine the probabilistic charac-teristics of 8-bit error-correcting codes. The principles of their coding and decoding are considered. Core results. The features of the developed identification protocol when transmitting packets over the transport protocols TCP and UDP are determined. Practical relevance. The application of the devel-oped protocol for identifying network devices of the Internet of things in local and global communication networks is proposed.

show abstract

Principle of Nand Flash Memory

Cited by 3 publications

References 12 publications

Compact thermally stable high voltage FinFET with 40 nm tox and lateral break-down >35 V for 3D NAND flash periphery application

Compact thermally stable high voltage FinFET with 40 nm tox and lateral break-down >35 V for 3D NAND flash periphery application

BOOSTER: Rethinking the erase operation of low-latency SSDs to achieve high throughput and less long latency

IoT Device Identification Protocol based on Degraded Flash Memory

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