Preventing Scan-Based Side-Channel Attacks by Scan Obfuscating with a Configurable Shift Register

Abstract

Scan test is widely used in integrated circuit test. However, the excellent observability and controllability provided by the scan test gives attackers an opportunity to obtain sensitive information by using scan design to threaten circuit security. Hence, the primary motivation of this paper is to improve the existing DFT technique, i.e., to enhance the chip security on the premise of guaranteeing test quality. In this paper, we propose a new scan design method against scan-based side-channel attack. In the proposed method, the encryption structure is adopted, which requires the correct test authorization code to carry out normal test operation. Without the correct test authorization, the attackers cannot obtain the desired scan data, preventing the scan-based side-channel attacks. Furthermore, the test authorization code is determined by the nonvolatile memory built into the chip to realize the inconsistency of the test authorization code for each chip.

A Novel Secure Scan Design Based on Delayed Physical Unclonable Function

“…While they bring convenience to human life, they also face a series of security problems, for instance, information theft, malicious attack, etc. Therefore, information security has attracted more and more attention, at the same time, many researchers take care of security of the underlying hardware [10][11][12].…”