Present and future of I/O-buffer behavioral macromodels

Abstract

International audienceModern Signal and Power Integrity (SI/PI) verification flows rely on accurate models for complex I/O-buffers that drive and receive electrical signals on high-speed channels. The sheer density of modern integrated circuits makes detailed transistor-level descriptions computationally cumbersome to the point where they become unusable for system-level simulations. Fortunately, transistor-level descriptions may be replaced with more compact representations that approximate the input/output buffers behavior with considerable accuracy while providing a simulation speedup of several orders of magnitude. Known as behavioral models, surrogate models or macromodels, these computationally efficient equivalents have become a de-facto industry standard in SI/PI simulations. This paper presents an overview of the state-of-the-art in I/O-buffer behavioral modeling, introducing the main features of both standard and emerging solutions. Open issues and future research directions are also discussed

Constructive Signal Approximations for Fast Transient Simulation of Coupled Channels

“…1 by the voltage v in (t). The model structure (2) is indeed a particular case of two well-established formats for behavioral transceiver representation, namel the IBIS standard and the MpiLog framework [4], [6], [8], [17], see also [23]. We recall that basic Mpilog models are written as time-varying combinations of two-piece dynamical submodels as…”

A Comprehensive and Modular Stochastic Modeling Framework for the Variability-Aware Assessment of Signal Integrity in High-Speed Links

“…The tree is driven at the input port by a behavioral macromodel of an I/O transceiver of a 512-Mb Flash memory chip, which produces a pulse with a risetime of 1 ns. The behavioral macromodel is obtained with the techniques in [18]- [20]. Each of the four output ports is terminated by a pair of diodes with saturation current I S = 50 pA, series resistance R S = 5 Ω, and junction capacitance C JO = 3 pF.…”

Power Supply- and Temperature-Aware I/O Buffer Model for Signal-Power Integrity Simulation

“…Signal and power integrity (SPI) assessment of high-speed digital communication input-output (I/O) links is important for the design analysis and verification of modern memory and chip-to-chip interfaces in order to figure out SPI problems at an early design stage [1][2][3][4][5][6][7][8][9][10][11]. The highspeed I/O link design has to also comply with certain specifications regarding the process, supply voltage, and temperature variation to obtain the target performance [12][13][14][15][16].…”

“…The I/O link is composed by an active nonlinear part representing the I/O buffers that bond the die to the passive package and the printed circuit board (PCB) interconnects in order to ensure reliable highspeed digital data communication between the integrated circuits (ICs) I/O ports of the DDR memory and CPU, as depicted in Figure 1. Since, I/O buffers are designed based on transistors, they are characterized by a nonlinear dynamic behavior which is usually the main cause of signal distortions under high data rate transmission (i.e., short rise and fall time) and simultaneous switching output (SSO) buffers which generate the bouncing of the on-chip supply and ground voltages (e.g., simultaneous switching noise (SSN)) [1,5,8].…”

“…Besides, the manufacturers are often reluctant to release SPICE TL models for general use [7][8][9][10][11]. Therefore, the effective behavioral modelling of I/O buffers is an appealing alternative that hides the intellectual property (IP) of the I/O buffer's circuit and enables a fast and accurate SPI transient simulation of the high-speed communication I/O links, [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16]. Recently, power-aware I/O buffer models were proposed by enhancing the nonlinear parametric and surrogate modelling approaches, [4][5][6][7][8][9] for SPI analysis.…”